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src/southbridge: Remove unnecessary whitespace 

Change-Id: Ibcac5dd60dc7da82bbeeb89ac445a5a1aa56ed3d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16852
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2016-10-02 12:30:06 +02:00 committed by Martin Roth
parent 7d87e767b6
commit 9344bde4fe
11 changed files with 27 additions and 27 deletions
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2
src/southbridge/amd/amd8111/ide.c
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@ -33,7 +33,7 @@ static void ide_init(struct device *dev)
pci_write_config16(dev, 0x40, word); pci_write_config16(dev, 0x40, word);
byte = 0x20 ; // Latency: 64-->32 byte = 0x20; // Latency: 64-->32
pci_write_config8(dev, 0xd, byte); pci_write_config8(dev, 0xd, byte);
word = 0x0f; word = 0x0f;

4
src/southbridge/amd/cimx/sb700/bootblock.c
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@ -29,7 +29,7 @@ static void sb700_enable_rom(void)
* BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
*/ */
dword = pci_io_read_config32(dev, 0x44); dword = pci_io_read_config32(dev, 0x44);
//dword |= (1<<6) | (1<<29) | (1<<30) ; //dword |= (1<<6) | (1<<29) | (1<<30);
/*Turn on all of LPC IO Port decode enable */ /*Turn on all of LPC IO Port decode enable */
dword = 0xffffffff; dword = 0xffffffff;
pci_io_write_config32(dev, 0x44, dword); pci_io_write_config32(dev, 0x44, dword);
@ -42,7 +42,7 @@ static void sb700_enable_rom(void)
* BIT21: Port Enable for Port 0x80 * BIT21: Port Enable for Port 0x80
*/ */
dword = pci_io_read_config32(dev, 0x48); dword = pci_io_read_config32(dev, 0x48);
dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21);
pci_io_write_config32(dev, 0x48, dword); pci_io_write_config32(dev, 0x48, dword);
/* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */

2
src/southbridge/amd/cimx/sb800/bootblock.c
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@ -28,7 +28,7 @@ static void enable_rom(void)
* BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
*/ */
dword = pci_io_read_config32(dev, 0x44); dword = pci_io_read_config32(dev, 0x44);
//dword |= (1<<6) | (1<<29) | (1<<30) ; //dword |= (1<<6) | (1<<29) | (1<<30);
/* Turn on all of LPC IO Port decode enable */ /* Turn on all of LPC IO Port decode enable */
dword = 0xffffffff; dword = 0xffffffff;
pci_io_write_config32(dev, 0x44, dword); pci_io_write_config32(dev, 0x44, dword);

24
src/southbridge/amd/cimx/sb800/fan.c
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@ -102,7 +102,7 @@ if (sb_chip->imc_fan_zone0_enabled) {
sb_config.Pecstruct.MSGFun81zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone0MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun81zone0MSGREG1 = IMC_ZONE0; sb_config.Pecstruct.MSGFun81zone0MSGREG1 = IMC_ZONE0;
message_ptr = &sb_config.Pecstruct.MSGFun81zone0MSGREG2; message_ptr = &sb_config.Pecstruct.MSGFun81zone0MSGREG2;
for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone0_config_vals[i]; *(message_ptr + i) = sb_chip->imc_zone0_config_vals[i];
/* EC LDN9 function 83 zone 0 - Temperature Thresholds */ /* EC LDN9 function 83 zone 0 - Temperature Thresholds */
@ -110,14 +110,14 @@ if (sb_chip->imc_fan_zone0_enabled) {
sb_config.Pecstruct.MSGFun83zone0MSGREG1 = IMC_ZONE0; sb_config.Pecstruct.MSGFun83zone0MSGREG1 = IMC_ZONE0;
sb_config.Pecstruct.MSGFun83zone0MSGREGB = 0x00; sb_config.Pecstruct.MSGFun83zone0MSGREGB = 0x00;
message_ptr = &sb_config.Pecstruct.MSGFun83zone0MSGREG2; message_ptr = &sb_config.Pecstruct.MSGFun83zone0MSGREG2;
for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone0_thresholds[i]; *(message_ptr + i) = sb_chip->imc_zone0_thresholds[i];
/*EC LDN9 function 85 zone 0 - Fan Speeds */ /*EC LDN9 function 85 zone 0 - Fan Speeds */
sb_config.Pecstruct.MSGFun85zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone0MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun85zone0MSGREG1 = IMC_ZONE0; sb_config.Pecstruct.MSGFun85zone0MSGREG1 = IMC_ZONE0;
message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2; message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2;
for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i]; *(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i];
} }
@ -133,7 +133,7 @@ if (sb_chip->imc_fan_zone1_enabled) {
sb_config.Pecstruct.MSGFun81zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone1MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun81zone1MSGREG1 = IMC_ZONE1; sb_config.Pecstruct.MSGFun81zone1MSGREG1 = IMC_ZONE1;
message_ptr = &sb_config.Pecstruct.MSGFun81zone1MSGREG2; message_ptr = &sb_config.Pecstruct.MSGFun81zone1MSGREG2;
for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone1_config_vals[i]; *(message_ptr + i) = sb_chip->imc_zone1_config_vals[i];
/* EC LDN9 function 83 zone 1 - Temperature Thresholds */ /* EC LDN9 function 83 zone 1 - Temperature Thresholds */
@ -141,14 +141,14 @@ if (sb_chip->imc_fan_zone1_enabled) {
sb_config.Pecstruct.MSGFun83zone1MSGREG1 = IMC_ZONE1; sb_config.Pecstruct.MSGFun83zone1MSGREG1 = IMC_ZONE1;
sb_config.Pecstruct.MSGFun83zone1MSGREGB = 0x00; sb_config.Pecstruct.MSGFun83zone1MSGREGB = 0x00;
message_ptr = &sb_config.Pecstruct.MSGFun83zone1MSGREG2; message_ptr = &sb_config.Pecstruct.MSGFun83zone1MSGREG2;
for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone1_thresholds[i]; *(message_ptr + i) = sb_chip->imc_zone1_thresholds[i];
/* EC LDN9 function 85 zone 1 - Fan Speeds */ /* EC LDN9 function 85 zone 1 - Fan Speeds */
sb_config.Pecstruct.MSGFun85zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone1MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun85zone1MSGREG1 = IMC_ZONE1; sb_config.Pecstruct.MSGFun85zone1MSGREG1 = IMC_ZONE1;
message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2; message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2;
for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i]; *(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i];
} }
@ -165,7 +165,7 @@ if (sb_chip->imc_fan_zone2_enabled) {
sb_config.Pecstruct.MSGFun81zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone2MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun81zone2MSGREG1 = IMC_ZONE2; sb_config.Pecstruct.MSGFun81zone2MSGREG1 = IMC_ZONE2;
message_ptr = &sb_config.Pecstruct.MSGFun81zone2MSGREG2; message_ptr = &sb_config.Pecstruct.MSGFun81zone2MSGREG2;
for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone2_config_vals[i]; *(message_ptr + i) = sb_chip->imc_zone2_config_vals[i];
/* EC LDN9 function 83 zone 2 */ /* EC LDN9 function 83 zone 2 */
@ -173,14 +173,14 @@ if (sb_chip->imc_fan_zone2_enabled) {
sb_config.Pecstruct.MSGFun83zone2MSGREG1 = IMC_ZONE2; sb_config.Pecstruct.MSGFun83zone2MSGREG1 = IMC_ZONE2;
sb_config.Pecstruct.MSGFun83zone2MSGREGB = 0x00; sb_config.Pecstruct.MSGFun83zone2MSGREGB = 0x00;
message_ptr = &sb_config.Pecstruct.MSGFun83zone2MSGREG2; message_ptr = &sb_config.Pecstruct.MSGFun83zone2MSGREG2;
for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone2_thresholds[i]; *(message_ptr + i) = sb_chip->imc_zone2_thresholds[i];
/* EC LDN9 function 85 zone 2 */ /* EC LDN9 function 85 zone 2 */
sb_config.Pecstruct.MSGFun85zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone2MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun85zone2MSGREG1 = IMC_ZONE2; sb_config.Pecstruct.MSGFun85zone2MSGREG1 = IMC_ZONE2;
message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2; message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2;
for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i]; *(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i];
} }
@ -197,7 +197,7 @@ if (sb_chip->imc_fan_zone3_enabled) {
sb_config.Pecstruct.MSGFun81zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone3MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun81zone3MSGREG1 = IMC_ZONE3; sb_config.Pecstruct.MSGFun81zone3MSGREG1 = IMC_ZONE3;
message_ptr = &sb_config.Pecstruct.MSGFun81zone3MSGREG2; message_ptr = &sb_config.Pecstruct.MSGFun81zone3MSGREG2;
for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone3_config_vals[i]; *(message_ptr + i) = sb_chip->imc_zone3_config_vals[i];
/* EC LDN9 function 83 zone 3 */ /* EC LDN9 function 83 zone 3 */
@ -205,14 +205,14 @@ if (sb_chip->imc_fan_zone3_enabled) {
sb_config.Pecstruct.MSGFun83zone3MSGREG1 = IMC_ZONE3; sb_config.Pecstruct.MSGFun83zone3MSGREG1 = IMC_ZONE3;
sb_config.Pecstruct.MSGFun83zone3MSGREGB = 0x00; sb_config.Pecstruct.MSGFun83zone3MSGREGB = 0x00;
message_ptr = &sb_config.Pecstruct.MSGFun83zone3MSGREG2; message_ptr = &sb_config.Pecstruct.MSGFun83zone3MSGREG2;
for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone3_thresholds[i]; *(message_ptr + i) = sb_chip->imc_zone3_thresholds[i];
/* EC LDN9 function 85 zone 3 */ /* EC LDN9 function 85 zone 3 */
sb_config.Pecstruct.MSGFun85zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone3MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun85zone3MSGREG1 = IMC_ZONE3; sb_config.Pecstruct.MSGFun85zone3MSGREG1 = IMC_ZONE3;
message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2; message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2;
for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i]; *(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i];
} }

4
src/southbridge/amd/cimx/sb900/bootblock.c
View File

@ -28,7 +28,7 @@ static void sb900_enable_rom(void)
* BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
*/ */
dword = pci_io_read_config32(dev, 0x44); dword = pci_io_read_config32(dev, 0x44);
//dword |= (1<<6) | (1<<29) | (1<<30) ; //dword |= (1<<6) | (1<<29) | (1<<30);
/*Turn on all of LPC IO Port decode enable */ /*Turn on all of LPC IO Port decode enable */
dword = 0xffffffff; dword = 0xffffffff;
pci_io_write_config32(dev, 0x44, dword); pci_io_write_config32(dev, 0x44, dword);
@ -41,7 +41,7 @@ static void sb900_enable_rom(void)
* BIT21: Port Enable for Port 0x80 * BIT21: Port Enable for Port 0x80
*/ */
dword = pci_io_read_config32(dev, 0x48); dword = pci_io_read_config32(dev, 0x48);
dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21);
pci_io_write_config32(dev, 0x48, dword); pci_io_write_config32(dev, 0x48, dword);
/* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */

2
src/southbridge/amd/rs780/gfx.c
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@ -302,7 +302,7 @@ static void poweron_ddi_lanes(device_t nb_dev)
ddi_pads = ~(nbpcie_ind_read_index(nb_dev, 0x65)); /* save original setting */ ddi_pads = ~(nbpcie_ind_read_index(nb_dev, 0x65)); /* save original setting */
gfx_cfg = nbmisc_read_index(nb_dev, 0x74); gfx_cfg = nbmisc_read_index(nb_dev, 0x74);
for (i = 0; i < 3 ; i++) { for (i = 0; i < 3; i++) {
if (gfx_cfg & GFX_CONFIG_DDI) { if (gfx_cfg & GFX_CONFIG_DDI) {
ddi_pads |= (3 << (i * 2)); ddi_pads |= (3 << (i * 2));
} }

2
src/southbridge/ricoh/rl5c476/rl5c476.c
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@ -184,7 +184,7 @@ static void rl5c476_set_resources(device_t dev)
if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
resource = find_resource(dev,1); resource = find_resource(dev,1);
if ( !(resource->flags & IORESOURCE_STORED) ){ if ( !(resource->flags & IORESOURCE_STORED) ){
resource->flags |= IORESOURCE_STORED ; resource->flags |= IORESOURCE_STORED;
printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base); printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base);
cf_base = resource->base; cf_base = resource->base;
} }

2
src/southbridge/sis/sis966/ide.c
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@ -133,7 +133,7 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n");
pci_write_config16(dev, 0x50, word); pci_write_config16(dev, 0x50, word);
byte = 0x20 ; // Latency: 64-->32 byte = 0x20; // Latency: 64-->32
pci_write_config8(dev, 0xd, byte); pci_write_config8(dev, 0xd, byte);
dword = pci_read_config32(dev, 0xf8); dword = pci_read_config32(dev, 0xf8);

6
src/southbridge/sis/sis966/nic.c
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@ -73,7 +73,7 @@ static void readApcMacAddr(void)
outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
printk(BIOS_DEBUG, "MAC addr in APC = "); printk(BIOS_DEBUG, "MAC addr in APC = ");
for (i = 0x9 ; i <=0xe ; i++) { for (i = 0x9; i <=0xe; i++) {
printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); printk(BIOS_DEBUG, "%2.2x",readApcByte(i));
} }
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");
@ -97,7 +97,7 @@ static void set_apc(struct device *dev)
outl(0x80001048,0xcf8); outl(0x80001048,0xcf8);
outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
for (i = 0 ; i <3; i++) { for (i = 0; i <3; i++) {
addr=0x9+2*i; addr=0x9+2*i;
writeApcByte(addr,(u8)(MacAddr[i]&0xFF)); writeApcByte(addr,(u8)(MacAddr[i]&0xFF));
writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF)); writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF));
@ -139,7 +139,7 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg)
mdelay(10); mdelay(10);
for (i=0 ; i <= LoopNum; i++) { for (i=0; i <= LoopNum; i++) {
ulValue=read32(base + 0x3c); ulValue=read32(base + 0x3c);
if (!(ulValue & 0x0080)) //BIT_7 if (!(ulValue & 0x0080)) //BIT_7

2
src/southbridge/via/vt8237r/early_smbus.c
View File

@ -347,7 +347,7 @@ int acpi_get_sleep_type(void)
tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
printk(BIOS_DEBUG, "%02x", tmp); printk(BIOS_DEBUG, "%02x", tmp);
return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0;
} }
#if defined(__GNUC__) #if defined(__GNUC__)

4
src/southbridge/via/vt8237r/lpc.c
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@ -51,7 +51,7 @@ static unsigned char *pin_to_irq(const unsigned char *pin)
{ {
static unsigned char Irqs[4]; static unsigned char Irqs[4];
int i; int i;
for (i = 0 ; i < 4 ; i++) for (i = 0; i < 4; i++)
Irqs[i] = pciIrqs[ pin[i] - 'A' ]; Irqs[i] = pciIrqs[ pin[i] - 'A' ];
return Irqs; return Irqs;
@ -253,7 +253,7 @@ static void setup_pm(device_t dev)
int acpi_get_sleep_type(void) int acpi_get_sleep_type(void)
{ {
u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0;
} }
static void vt8237r_init(struct device *dev) static void vt8237r_init(struct device *dev)