mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.

TEST=Set MAX_CPUS=2 and run qemu with -smp 2

Signed-off-by: Philipp Hug <philipp@hug.cx>
Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xiang Wang <merle@hardenedlinux.org>

src/mainboard/emulation/qemu-riscv/Makefile.inc

@@ -19,6 +19,7 @@ bootblock-y += clint.c
 romstage-y += romstage.c
 romstage-y += uart.c
 romstage-y += rom_media.c
+romstage-y += clint.c
 
 ramstage-y += uart.c
 ramstage-y += rom_media.c

src/mainboard/emulation/qemu-riscv/clint.c

@@ -14,6 +14,7 @@
  */
 
 #include <mcall.h>
+#include <device/mmio.h>
 #include <mainboard/addressmap.h>
 
 /* This function is used to initialize HLS()->time/HLS()->timecmp  */
@@ -23,3 +24,8 @@ void mtime_init(void)
 	HLS()->time = (uint64_t *)(QEMU_VIRT_CLINT + 0xbff8);
 	HLS()->timecmp = (uint64_t *)(QEMU_VIRT_CLINT + 0x4000 + 8 * hart_id);
 }
+
+void set_msip(int hartid, int val)
+{
+	write32((void *)(QEMU_VIRT_CLINT + 4 * (uintptr_t)hartid), !!val);
+}

src/mainboard/emulation/spike-riscv/Makefile.inc

@@ -18,6 +18,7 @@ bootblock-y += clint.c
 romstage-y += romstage.c
 romstage-y += uart.c
 romstage-y += rom_media.c
+romstage-y += clint.c
 ramstage-y += uart.c
 ramstage-y += rom_media.c
 ramstage-y += clint.c

src/mainboard/emulation/spike-riscv/clint.c

@@ -14,6 +14,7 @@
  */
 
 #include <mcall.h>
+#include <device/mmio.h>
 
 #define SPIKE_CLINT_BASE	0x02000000
 
@@ -24,3 +25,8 @@ void mtime_init(void)
 	HLS()->time = (uint64_t *)(SPIKE_CLINT_BASE + 0xbff8);
 	HLS()->timecmp = (uint64_t *)(SPIKE_CLINT_BASE + 0x4000 + 8 * hart_id);
 }
+
+void set_msip(int hartid, int val)
+{
+	write32((void *)(SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val);
+}

src/soc/ucb/riscv/Makefile.inc

@@ -1,11 +1,7 @@
 ifeq ($(CONFIG_SOC_UCB_RISCV),y)
 
-bootblock-y += ipi.c
-
 romstage-y += cbmem.c
-romstage-y += ipi.c
 
 ramstage-y += cbmem.c
-ramstage-y += ipi.c
 
 endif

src/soc/ucb/riscv/ipi.c

@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 HardenedLinux
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <mcall.h>
-
-/* TODO: Please implement this function */
-void set_msip(int hartid, int val)
-{
-}