From 93632a9f1fdbece6cfb1501520005a3c952c8841 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Fri, 4 Jun 2021 14:09:13 +0530
Subject: [PATCH] mb/intel/sm: Skip FSP to program UART0

Set "SerialIoUartMode" for UART0 as PchSerialIoSkipInit

Change-Id: Idc7da7bf38634c04b0f4acd4c7c2ea9fa88545e5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55207
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/shadowmountain/variants/baseboard/devicetree.cb       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index d5e5951c2a..ab2c915488 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -103,7 +103,7 @@ chip soc/intel/alderlake
 	}"
 
 	register "SerialIoUartMode" = "{
-		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
 	}"