Fix ICH spi implementation which reads data from different chips.
This patch adjusts the read timeout in order to support flash chips which needs more than 60ms to complete a spi command. This problem can be reproduced on a Thinkpad T520 with M25PX64 spi chip ( suspend to ram bug ). Change-Id: I22b2e59f1855ead6162a292b83b9b854b55c0235 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: http://review.coreboot.org/7105 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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@ -517,7 +517,7 @@ static int spi_setup_offset(spi_transaction *trans)
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}
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/*
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* Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set
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* Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
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* below is True) or 0. In case the wait was for the bit(s) to set - write
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* those bits back, which would cause resetting them.
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*
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@ -525,7 +525,7 @@ static int spi_setup_offset(spi_transaction *trans)
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*/
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static int ich_status_poll(u16 bitmask, int wait_til_set)
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{
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int timeout = 6000; /* This will result in 60 ms */
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int timeout = 600000; /* This will result in 6 seconds */
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u16 status = 0;
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while (timeout--) {
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@ -538,7 +538,7 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
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udelay(10);
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}
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printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n",
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printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, bitmask %x\n",
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status, bitmask);
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return -1;
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}
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