GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/stoneyridge: Add IO access functions for PMx 

Replace locations in the source that explicitely use the CD6/CD7
index/data pair with utility function calls.

Change-Id: I6e7ba472ef2551e363987d18a79408fcd2074de4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson 2019-05-05 15:39:40 -06:00 committed by Martin Roth
parent f36fcdf2ab
commit 939bfccb3d
4 changed files with 48 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/soc/amd/stoneyridge/enable_usbdebug.c
View File

@ -26,10 +26,7 @@
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
/* Enable all of the USB controllers */
outb(PM_USB_ENABLE, PM_INDEX);
outb(PM_USB_ALL_CONTROLLERS, PM_DATA);
pm_io_write8(PM_USB_ENABLE, PM_USB_ALL_CONTROLLERS);
return SOC_EHCI1_DEV;
}

6
src/soc/amd/stoneyridge/include/soc/southbridge.h
View File

@ -491,6 +491,12 @@ void sb_tpm_decode(void);
void sb_tpm_decode_spi(void);
void lpc_wideio_512_window(uint16_t base);
void lpc_wideio_16_window(uint16_t base);
uint8_t pm_io_read8(uint8_t reg);
uint16_t pm_io_read16(uint8_t reg);
uint32_t pm_io_read32(uint8_t reg);
void pm_io_write8(uint8_t reg, uint8_t value);
void pm_io_write16(uint8_t reg, uint16_t value);
void pm_io_write32(uint8_t reg, uint32_t value);
u8 pm_read8(u8 reg);
u16 pm_read16(u8 reg);
u32 pm_read32(u8 reg);

37
src/soc/amd/stoneyridge/sb_util.c
View File

@ -18,6 +18,43 @@
#include <arch/acpi.h>
#include <soc/southbridge.h>
/* PM registers are accessed a byte at a time via CD6/CD7 */
uint8_t pm_io_read8(uint8_t reg)
{
outb(reg, PM_INDEX);
return inb(PM_DATA);
}
uint16_t pm_io_read16(uint8_t reg)
{
return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg);
}
uint32_t pm_io_read32(uint8_t reg)
{
return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg);
}
void pm_io_write8(uint8_t reg, uint8_t value)
{
outb(reg, PM_INDEX);
outb(value, PM_DATA);
}
void pm_io_write16(uint8_t reg, uint16_t value)
{
pm_io_write8(reg, value & 0xff);
value >>= 8;
pm_io_write8(reg + sizeof(uint8_t), value & 0xff);
}
void pm_io_write32(uint8_t reg, uint32_t value)
{
pm_io_write16(reg, value & 0xffff);
value >>= 16;
pm_io_write16(reg + sizeof(uint16_t), value & 0xffff);
}
/* smbus pci read/write - access registers at 0xfed80000 - currently unused */
/* smi read/write - access registers at 0xfed80200 */

12
src/soc/amd/stoneyridge/southbridge.c
View File

@ -329,11 +329,9 @@ void sb_lpc_port80(void)
u8 byte;
/* Enable LPC controller */
outb(PM_LPC_GATING, PM_INDEX);
byte = inb(PM_DATA);
byte = pm_io_read8(PM_LPC_GATING);
byte |= PM_LPC_ENABLE;
outb(PM_LPC_GATING, PM_INDEX);
outb(byte, PM_DATA);
pm_io_write8(PM_LPC_GATING, byte);
/* Enable port 80 LPC decode in pci function 3 configuration space. */
byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH);
@ -367,11 +365,9 @@ void sb_acpi_mmio_decode(void)
uint8_t byte;
/* Enable ACPI MMIO range 0xfed80000 - 0xfed81fff */
outb(PM_ISA_CONTROL, PM_INDEX);
byte = inb(PM_DATA);
byte = pm_io_read8(PM_ISA_CONTROL);
byte |= MMIO_EN;
outb(PM_ISA_CONTROL, PM_INDEX);
outb(byte, PM_DATA);
pm_io_write8(PM_ISA_CONTROL, byte);
}
static void sb_enable_cf9_io(void)