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nb/intel/x4x: Correct and use macros for CLKCFG 

The `CLKCFG_UPDATE` macro is copied from gm45 and unused. Correct it and
use the CLKCFG macros instead of magic values.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: I17e972eba21282ac84c7afe10b7149cd1131fd07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51877
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-03-27 09:06:54 +01:00 committed by Nico Huber
parent 70dc0a8cc3
commit 93aab51ec1
4 changed files with 7 additions and 6 deletions
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2
src/northbridge/intel/x4x/early_init.c
View File

@ -62,7 +62,7 @@ static void init_egress(void)
EPBAR8(EPVC0RCTL) = 1;
EPBAR8(EPPVCCAP1) = 1;
switch (MCHBAR32(0xc00) & 0x7) {
switch (MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) {
case 0x0:
/* FSB 1066 */
EPBAR32(EPVC1ITC) = 0x0001a6db;

2
src/northbridge/intel/x4x/raminit.c
View File

@ -412,7 +412,7 @@ static void print_selected_timings(struct sysinfo *s)
static void find_fsb_speed(struct sysinfo *s)
{
switch (MCHBAR32(0xc00) & 0x7) {
switch ((MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) >> CLKCFG_FSBCLK_SHIFT) {
case 0x0:
s->max_fsb = FSB_CLOCK_1066MHz;
break;

7
src/northbridge/intel/x4x/raminit_ddr23.c
View File

@ -1952,11 +1952,12 @@ void do_raminit(struct sysinfo *s, int fast_boot)
MCHBAR8_OR(0x1a8, 0x4);
/* Set frequency */
MCHBAR32_AND_OR(0xc00, ~0x70,
(s->selected_timings.mem_clk << 4) | (1 << 10));
MCHBAR32_AND_OR(CLKCFG_MCHBAR, ~CLKCFG_MEMCLK_MASK,
(s->selected_timings.mem_clk << CLKCFG_MEMCLK_SHIFT) | CLKCFG_UPDATE);
/* Overwrite value if chipset rejects it */
s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4;
s->selected_timings.mem_clk =
(MCHBAR8(CLKCFG_MCHBAR) & CLKCFG_MEMCLK_MASK) >> CLKCFG_MEMCLK_SHIFT;
if (s->selected_timings.mem_clk > (s->max_fsb + 3))
die("Error: DDR is faster than FSB, halt\n");
}

2
src/northbridge/intel/x4x/x4x.h
View File

@ -74,7 +74,7 @@
#define CLKCFG_FSBCLK_MASK (7 << CLKCFG_FSBCLK_SHIFT)
#define CLKCFG_MEMCLK_SHIFT 4
#define CLKCFG_MEMCLK_MASK (7 << CLKCFG_MEMCLK_SHIFT)
#define CLKCFG_UPDATE (1 << 12)
#define CLKCFG_UPDATE (1 << 10)
#define SSKPD_MCHBAR 0x0c20 /* 64 bit */