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Intel e7505: build as separate object file 

No longer include northbridge files directly in the source for
mainboard romstage.c and fix includes.

Also make required adjustments to function declarations.

Change-Id: Iafdcc0766ed44c64cc628e5935eef2c6372f5f22
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/906
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Kyösti Mälkki 2012-04-18 21:13:33 +03:00 committed by Patrick Georgi
parent 97c064f034
commit 93b4ed91f6
6 changed files with 65 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/mainboard/aopen/dxplplusu/romstage.c
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@ -20,33 +20,28 @@
#include <stdint.h> #include <stdint.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h> #include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <stdlib.h> #include <stdlib.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <spd.h>
#include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/i82801dx.h"
#include "southbridge/intel/i82801dx/early_smbus.c" #include "southbridge/intel/i82801dx/early_smbus.c"
#include "southbridge/intel/i82801dx/reset.c" #include "southbridge/intel/i82801dx/reset.c"
#include "northbridge/intel/e7505/raminit.h" #include "northbridge/intel/e7505/raminit.h"
#include "northbridge/intel/e7505/debug.c"
#include <device/pnp_def.h>
#include "superio/smsc/lpc47m10x/early_serial.c" #include "superio/smsc/lpc47m10x/early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) #define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1)
static inline int spd_read_byte(unsigned device, unsigned address) int spd_read_byte(unsigned device, unsigned address)
{ {
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#include "northbridge/intel/e7505/raminit.c"
void main(unsigned long bist) void main(unsigned long bist)
{ {
static const struct mem_controller memctrl[] = { static const struct mem_controller memctrl[] = {
@ -66,7 +61,7 @@ void main(unsigned long bist)
report_bist_failure(bist); report_bist_failure(bist);
// If this is a warm boot, some initialization can be skipped // If this is a warm boot, some initialization can be skipped
if (!bios_reset_detected()) { if (!e7505_mch_is_ready()) {
enable_smbus(); enable_smbus();
/* The real MCH initialisation. */ /* The real MCH initialisation. */

2
src/northbridge/intel/e7505/Makefile.inc
View File

@ -1 +1,3 @@
ramstage-y += northbridge.c ramstage-y += northbridge.c
romstage-y += raminit.c
romstage-y += debug.c

40
src/northbridge/intel/e7505/debug.c
View File

@ -1,9 +1,20 @@
#include <device/pci_def.h>
#include <console/console.h>
#include <stdlib.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <spd.h>
#include "raminit.h"
#include "debug.h"
/* /*
* generic debug code, used by mainboard specific romstage.c * generic debug code, used by mainboard specific romstage.c
* *
*/ */
#if 1
static void print_debug_pci_dev(unsigned dev) void print_debug_pci_dev(unsigned dev)
{ {
print_debug("PCI: "); print_debug("PCI: ");
print_debug_hex8((dev >> 16) & 0xff); print_debug_hex8((dev >> 16) & 0xff);
@ -13,7 +24,7 @@ static void print_debug_pci_dev(unsigned dev)
print_debug_hex8((dev >> 8) & 7); print_debug_hex8((dev >> 8) & 7);
} }
static inline void print_pci_devices(void) void print_pci_devices(void)
{ {
device_t dev; device_t dev;
for(dev = PCI_DEV(0, 0, 0); for(dev = PCI_DEV(0, 0, 0);
@ -31,7 +42,7 @@ static inline void print_pci_devices(void)
} }
} }
static void dump_pci_device(unsigned dev) void dump_pci_device(unsigned dev)
{ {
int i; int i;
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
@ -58,7 +69,7 @@ static void dump_pci_device(unsigned dev)
print_debug("\n"); print_debug("\n");
} }
static inline void dump_pci_devices(void) void dump_pci_devices(void)
{ {
device_t dev; device_t dev;
for(dev = PCI_DEV(0, 0, 0); for(dev = PCI_DEV(0, 0, 0);
@ -75,7 +86,7 @@ static inline void dump_pci_devices(void)
} }
} }
static inline void dump_pci_devices_on_bus(unsigned busn) void dump_pci_devices_on_bus(unsigned busn)
{ {
device_t dev; device_t dev;
for(dev = PCI_DEV(busn, 0, 0); for(dev = PCI_DEV(busn, 0, 0);
@ -92,7 +103,7 @@ static inline void dump_pci_devices_on_bus(unsigned busn)
} }
} }
static inline void dump_spd_registers(const struct mem_controller *ctrl) void dump_spd_registers(const struct mem_controller *ctrl)
{ {
int i; int i;
print_debug("\n"); print_debug("\n");
@ -121,7 +132,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
print_debug(": "); print_debug(": ");
#endif #endif
} }
status = smbus_read_byte(device, j); status = spd_read_byte(device, j);
if (status < 0) { if (status < 0) {
break; break;
} }
@ -158,7 +169,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
print_debug(": "); print_debug(": ");
#endif #endif
} }
status = smbus_read_byte(device, j); status = spd_read_byte(device, j);
if (status < 0) { if (status < 0) {
break; break;
} }
@ -174,13 +185,13 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
} }
} }
} }
static inline void dump_smbus_registers(void) void dump_smbus_registers(void)
{ {
unsigned device; unsigned device;
print_debug("\n"); print_debug("\n");
for(device = 1; device < 0x80; device++) { for(device = 1; device < 0x80; device++) {
int j; int j;
if( smbus_read_byte(device, 0) < 0 ) continue; if( spd_read_byte(device, 0) < 0 ) continue;
#if !defined(__ROMCC__) #if !defined(__ROMCC__)
printk(BIOS_DEBUG, "smbus: %02x", device); printk(BIOS_DEBUG, "smbus: %02x", device);
#else #else
@ -190,7 +201,7 @@ static inline void dump_smbus_registers(void)
for(j = 0; j < 256; j++) { for(j = 0; j < 256; j++) {
int status; int status;
unsigned char byte; unsigned char byte;
status = smbus_read_byte(device, j); status = spd_read_byte(device, j);
if (status < 0) { if (status < 0) {
break; break;
} }
@ -215,7 +226,7 @@ static inline void dump_smbus_registers(void)
} }
} }
static inline void dump_io_resources(unsigned port) void dump_io_resources(unsigned port)
{ {
int i; int i;
@ -249,7 +260,7 @@ static inline void dump_io_resources(unsigned port)
} }
} }
static inline void dump_mem(unsigned start, unsigned end) void dump_mem(unsigned start, unsigned end)
{ {
unsigned i; unsigned i;
print_debug("dump_mem:"); print_debug("dump_mem:");
@ -272,4 +283,3 @@ static inline void dump_mem(unsigned start, unsigned end)
} }
print_debug("\n"); print_debug("\n");
} }
#endif

15
src/northbridge/intel/e7505/debug.h Normal file
View File

@ -0,0 +1,15 @@
#ifndef E7505_DEBUG_H
#define E7505_DEBUG_H
void print_debug_pci_dev(unsigned dev);
void print_pci_devices(void);
void dump_pci_device(unsigned dev);
void dump_pci_devices(void);
void dump_pci_devices_on_bus(unsigned busn);
void dump_spd_registers(const struct mem_controller *ctrl);
void dump_smbus_registers(void);
void dump_io_resources(unsigned port);
void dump_mem(unsigned start, unsigned end);
#endif

15
src/northbridge/intel/e7505/raminit.c
View File

@ -11,14 +11,25 @@
/* converted to C 6/2004 yhlu */ /* converted to C 6/2004 yhlu */
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <arch/cpu.h>
#include <stdlib.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <assert.h> #include <assert.h>
#include <spd.h> #include <spd.h>
#include <sdram_mode.h> #include <sdram_mode.h>
#include <stdlib.h>
#include "raminit.h"
#include "e7505.h" #include "e7505.h"
#include "debug.h"
/*----------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
Definitions: Definitions:
@ -1899,7 +1910,7 @@ void e7505_mch_done(const struct mem_controller *memctrl)
DUMPNORTH(); DUMPNORTH();
} }
static int bios_reset_detected(void) int e7505_mch_is_ready(void)
{ {
uint32_t dword = pci_read_config32(MCHDEV, DRC); uint32_t dword = pci_read_config32(MCHDEV, DRC);
return !!(dword & DRC_DONE); return !!(dword & DRC_DONE);

5
src/northbridge/intel/e7505/raminit.h
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@ -18,5 +18,10 @@ struct mem_controller {
void e7505_mch_init(const struct mem_controller *memctrl); void e7505_mch_init(const struct mem_controller *memctrl);
void e7505_mch_scrub_ecc(unsigned long ret_addr); void e7505_mch_scrub_ecc(unsigned long ret_addr);
void e7505_mch_done(const struct mem_controller *memctrl); void e7505_mch_done(const struct mem_controller *memctrl);
int e7505_mch_is_ready(void);
/* Mainboard exports this. */
int spd_read_byte(unsigned device, unsigned address);
#endif /* RAMINIT_H */ #endif /* RAMINIT_H */