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mb/google/brya: Fix Idle S0ix issue due to dynamic GPIO PM disabled 

GPIO PM was disabled for brya to evaluate if longer interrupt pulses
are required for ADL. Since ADL requires 4us long pulses (EDS:626817),
GPIO PM can be enabled. All devices currently tested on brya support 4us
long pulses. This change drops the GPIO PM override and re-enables
dynamic GPIO PM.

TEST=Boot brya to OS, ensure no TPM errors.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0c7b66b5514d8b80775ab7578ce7b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56926
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Meera Ravindranath 2021-08-12 12:17:28 +05:30 committed by Tim Wawrzynczak
parent 1f84b2c025
commit 93ca873f20
1 changed files with 0 additions and 11 deletions
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11
src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
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@ -24,17 +24,6 @@ chip soc/intel/alderlake
# Enable heci communication
register "HeciEnabled" = "1"
# This disabled autonomous GPIO power management, otherwise
# old cr50 FW only supports short pulses; need to clarify
# the minimum PCH IRQ pulse width with Intel, b/180111628
register "gpio_override_pm" = "1"
register "gpio_pm[COMM_0]" = "0"
register "gpio_pm[COMM_1]" = "0"
register "gpio_pm[COMM_2]" = "0"
register "gpio_pm[COMM_3]" = "0"
register "gpio_pm[COMM_4]" = "0"
register "gpio_pm[COMM_5]" = "0"
# Enable CNVi BT
register "CnviBtCore" = "true"