soc/intel/apollolake: Use common PMC for apollolake
With this patch apollolake uses the common PMC util code.No regression observed on a APL platform. Change-Id: I322a25a8b608d7fe98bec626c6696e723357a9d2 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/19375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Shaunak Saha
Aaron Durbin
parent
83e9823aec
commit
93cdc8bbc2
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@ -72,6 +72,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_I2C
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select SOC_INTEL_COMMON_BLOCK_LPSS
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select SOC_INTEL_COMMON_BLOCK_PCR
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select SOC_INTEL_COMMON_BLOCK_PMC
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select SOC_INTEL_COMMON_BLOCK_RTC
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_SCS
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@ -22,6 +22,7 @@
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#include <intelblocks/pcr.h>
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#include <intelblocks/rtc.h>
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#include <intelblocks/systemagent.h>
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#include <intelblocks/pmclib.h>
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#include <soc/iomap.h>
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#include <soc/cpu.h>
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#include <soc/gpio.h>
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@ -91,7 +92,7 @@ void bootblock_soc_early_init(void)
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enable_pmcbar();
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/* Clear global reset promotion bit */
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global_reset_enable(0);
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pmc_global_reset_enable(0);
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/* Prepare UART for serial console. */
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if (IS_ENABLED(CONFIG_SOC_UART_DEBUG))
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@ -31,6 +31,7 @@
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#include <fsp/util.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/itss.h>
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#include <intelblocks/pmclib.h>
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#include <romstage_handoff.h>
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#include <soc/iomap.h>
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#include <soc/itss.h>
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@ -326,9 +327,9 @@ static void soc_final(void *data)
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rdev_munmap(&vbt_rdev, vbt);
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/* Disable global reset, just in case */
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global_reset_enable(0);
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pmc_global_reset_enable(0);
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/* Make sure payload/OS can't trigger global reset */
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global_reset_lock();
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pmc_global_reset_lock();
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}
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static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig)
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@ -136,4 +136,5 @@
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#define GPE0_DW3_30 126
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#define GPE0_DW3_31 127
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#define GPE_MAX GPE0_DW3_31
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#endif
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@ -21,6 +21,8 @@
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#include <stdint.h>
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#include <compiler.h>
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#include <arch/acpi.h>
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#include <soc/gpe.h>
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#include <soc/iomap.h>
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/* ACPI_BASE_ADDRESS */
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@ -135,6 +137,7 @@
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#define GPE0_B 1
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#define GPE0_C 2
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#define GPE0_D 3
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#define GPE_STD GPE0_A
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#define SATA_PME_STS (1 << 17)
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#define SMB_WAK_STS (1 << 16)
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#define AVS_PME_STS (1 << 14)
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@ -176,9 +179,7 @@
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# define CF9_GLB_RST (1 << 20)
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#define GPIO_GPE_CFG 0x1050
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#define GPE0_DWX_MASK 0xf
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#define GPE0_DW1_SHIFT 4
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#define GPE0_DW2_SHIFT 8
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#define GPE0_DW3_SHIFT 12
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#define GPE0_DW_SHIFT(x) (4 + 4*(x))
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#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
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#define PMC_GPE_N_95_64 8
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@ -216,33 +217,6 @@ struct chipset_power_state {
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uint32_t prev_sleep_state;
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} __packed;
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int fill_power_state(struct chipset_power_state *ps);
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int chipset_prev_sleep_state(struct chipset_power_state *ps);
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/* Rewrite the gpe0 registers in cbmem to proper values as per routing table */
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void fixup_power_state(void);
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/* Power Management Utility Functions. */
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uint32_t clear_smi_status(void);
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uint16_t clear_pm1_status(void);
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uint32_t clear_tco_status(void);
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uint32_t clear_gpe_status(void);
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void clear_pmc_status(void);
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void clear_gpi_gpe_sts(void);
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uint32_t get_smi_en(void);
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void enable_smi(uint32_t mask);
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void disable_smi(uint32_t mask);
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void enable_pm1(uint16_t events);
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void enable_pm1_control(uint32_t mask);
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void disable_pm1_control(uint32_t mask);
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void enable_gpe(uint32_t mask);
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void disable_gpe(uint32_t mask);
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void disable_all_gpe(void);
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uintptr_t get_pmc_mmio_bar(void);
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void pmc_gpe_init(void);
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void global_reset_enable(bool enable);
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void global_reset_lock(void);
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void pch_log_state(void);
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void enable_pm_timer_emulation(void);
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@ -20,6 +20,7 @@
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#include <device/pci_ids.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <intelblocks/pmclib.h>
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#include <soc/iomap.h>
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#include <soc/gpio.h>
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#include <soc/pci_devs.h>
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@ -128,7 +129,7 @@ static int choose_slp_s3_assertion_width(int width_usecs)
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static void set_slp_s3_assertion_width(int width_usecs)
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{
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uint32_t reg;
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uintptr_t gen_pmcon3 = get_pmc_mmio_bar() + GEN_PMCON3;
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uintptr_t gen_pmcon3 = soc_read_pmc_base() + GEN_PMCON3;
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int setting = choose_slp_s3_assertion_width(width_usecs);
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reg = read32((void *)gen_pmcon3);
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@ -143,7 +144,7 @@ static void pmc_init(struct device *dev)
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/* Set up GPE configuration */
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pmc_gpe_init();
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fixup_power_state();
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pmc_fixup_power_state();
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pch_set_acpi_mode();
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if (cfg != NULL)
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@ -153,7 +154,7 @@ static void pmc_init(struct device *dev)
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pch_log_state();
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/* Now that things have been logged clear out the PMC state. */
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clear_pmc_status();
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pmc_clear_status();
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}
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static const struct device_operations device_ops = {
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@ -20,20 +20,18 @@
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <cbmem.h>
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#include <cpu/x86/msr.h>
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#include <rules.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <halt.h>
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#include <intelblocks/msr.h>
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#include <intelblocks/pmclib.h>
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#include <rules.h>
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#include <soc/iomap.h>
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#include <soc/cpu.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <timer.h>
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#include <vboot/vboot_common.h>
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#include "chip.h"
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static uintptr_t read_pmc_mmio_bar(void)
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@ -41,32 +39,14 @@ static uintptr_t read_pmc_mmio_bar(void)
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return PMC_BAR0;
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}
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uintptr_t get_pmc_mmio_bar(void)
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uintptr_t soc_read_pmc_base(void)
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{
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return read_pmc_mmio_bar();
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}
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static void print_num_status_bits(int num_bits, uint32_t status,
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const char * const bit_names[])
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const char *const *soc_smi_sts_array(size_t *a)
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{
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int i;
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if (!status)
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return;
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for (i = num_bits - 1; i >= 0; i--) {
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if (status & (1 << i)) {
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if (bit_names[i])
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printk(BIOS_DEBUG, "%s ", bit_names[i]);
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else
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printk(BIOS_DEBUG, "BIT%d ", i);
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}
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}
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}
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static uint32_t print_smi_status(uint32_t smi_sts)
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{
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static const char * const smi_sts_bits[] = {
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static const char *const smi_sts_bits[] = {
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[BIOS_SMI_STS] = "BIOS",
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[LEGACY_USB_SMI_STS] = "LEGACY USB",
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[SLP_SMI_STS] = "SLP_SMI",
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@ -90,188 +70,44 @@ static uint32_t print_smi_status(uint32_t smi_sts)
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[PMC_OCP_SMI_STS] = "OCP_CSE",
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};
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if (!smi_sts)
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return 0;
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printk(BIOS_DEBUG, "SMI_STS: ");
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print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits);
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printk(BIOS_DEBUG, "\n");
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return smi_sts;
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*a = ARRAY_SIZE(smi_sts_bits);
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return smi_sts_bits;
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}
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static uint32_t reset_smi_status(void)
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/*
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* For APL/GLK this check for power button status if nothing else
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* is indicating an SMI and SMIs aren't turned into SCIs.
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* Apparently, there is no PM1 status bit in the SMI status
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* register. That makes things difficult for
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* determining if the power button caused an SMI.
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*/
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uint32_t soc_get_smi_status(uint32_t generic_sts)
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{
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uint32_t smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS);
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outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS);
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return smi_sts;
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}
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uint32_t clear_smi_status(void)
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{
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uint32_t sts = reset_smi_status();
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/*
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* Check for power button status if nothing else is indicating an SMI
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* and SMIs aren't turned into SCIs. Apparently, there is no PM1 status
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* bit in the SMI status register. That makes things difficult for
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* determining if the power button caused an SMI.
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*/
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if (sts == 0 && !(inl(ACPI_BASE_ADDRESS + PM1_CNT) & SCI_EN)) {
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if (generic_sts == 0 && !(inl(ACPI_BASE_ADDRESS + PM1_CNT) & SCI_EN)) {
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uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
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/* Fake PM1 status bit if power button pressed. */
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if (pm1_sts & PWRBTN_STS)
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sts |= (1 << FAKE_PM1_SMI_STS);
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generic_sts |= (1 << FAKE_PM1_SMI_STS);
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}
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return print_smi_status(sts);
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return generic_sts;
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}
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uint32_t get_smi_en(void)
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const char *const *soc_tco_sts_array(size_t *a)
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{
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return inl(ACPI_BASE_ADDRESS + SMI_EN);
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}
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void enable_smi(uint32_t mask)
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{
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uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
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smi_en |= mask;
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outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
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}
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void disable_smi(uint32_t mask)
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{
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uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
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smi_en &= ~mask;
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outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
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}
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void enable_pm1_control(uint32_t mask)
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{
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uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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pm1_cnt |= mask;
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outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
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}
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void disable_pm1_control(uint32_t mask)
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{
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uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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pm1_cnt &= ~mask;
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outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
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}
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static uint16_t reset_pm1_status(void)
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{
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uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
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outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS);
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return pm1_sts;
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}
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static uint16_t print_pm1_status(uint16_t pm1_sts)
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{
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static const char * const pm1_sts_bits[] = {
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[0] = "TMROF",
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[5] = "GBL",
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[8] = "PWRBTN",
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[10] = "RTC",
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[11] = "PRBTNOR",
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[13] = "USB",
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[14] = "PCIEXPWAK",
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[15] = "WAK",
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};
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if (!pm1_sts)
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return 0;
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printk(BIOS_SPEW, "PM1_STS: ");
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print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits);
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printk(BIOS_SPEW, "\n");
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return pm1_sts;
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}
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uint16_t clear_pm1_status(void)
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{
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return print_pm1_status(reset_pm1_status());
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}
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void enable_pm1(uint16_t events)
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{
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outw(events, ACPI_BASE_ADDRESS + PM1_EN);
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}
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static uint32_t print_tco_status(uint32_t tco_sts)
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{
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static const char * const tco_sts_bits[] = {
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static const char *const tco_sts_bits[] = {
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[3] = "TIMEOUT",
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[17] = "SECOND_TO",
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};
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if (!tco_sts)
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return 0;
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printk(BIOS_DEBUG, "TCO_STS: ");
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print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits);
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printk(BIOS_DEBUG, "\n");
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return tco_sts;
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*a = ARRAY_SIZE(tco_sts_bits);
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return tco_sts_bits;
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}
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static uint32_t reset_tco_status(void)
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const char *const *soc_gpe_sts_array(size_t *a)
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{
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uint32_t tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
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uint32_t tco_en = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
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outl(tco_sts, ACPI_BASE_ADDRESS + TCO_STS);
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return tco_sts & tco_en;
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}
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uint32_t clear_tco_status(void)
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{
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return print_tco_status(reset_tco_status());
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}
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void enable_gpe(uint32_t mask)
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{
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uint32_t gpe0a_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
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gpe0a_en |= mask;
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outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0_EN(0));
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}
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void disable_gpe(uint32_t mask)
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{
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uint32_t gpe0a_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
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gpe0a_en &= ~mask;
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outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0_EN(0));
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}
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void disable_all_gpe(void)
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{
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disable_gpe(~0);
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}
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/* Clear the gpio gpe0 status bits in ACPI registers */
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void clear_gpi_gpe_sts(void)
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{
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int i;
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for (i = 1; i < GPE0_REG_MAX; i++) {
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uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(i));
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outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(i));
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}
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}
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static uint32_t reset_gpe_status(void)
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{
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uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
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outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(0));
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return gpe_sts;
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}
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static uint32_t print_gpe_sts(uint32_t gpe_sts)
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{
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static const char * const gpe_sts_bits[] = {
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static const char *const gpe_sts_bits[] = {
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[0] = "PCIE_SCI",
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[2] = "SWGPE",
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[3] = "PCIE_WAKE0",
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@ -290,219 +126,30 @@ static uint32_t print_gpe_sts(uint32_t gpe_sts)
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[17] = "SATA_PME",
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};
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if (!gpe_sts)
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return gpe_sts;
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printk(BIOS_DEBUG, "GPE0a_STS: ");
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||||
print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits);
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
|
||||
return gpe_sts;
|
||||
*a = ARRAY_SIZE(gpe_sts_bits);
|
||||
return gpe_sts_bits;
|
||||
}
|
||||
|
||||
uint32_t clear_gpe_status(void)
|
||||
uint32_t soc_reset_tco_status(void)
|
||||
{
|
||||
return print_gpe_sts(reset_gpe_status());
|
||||
uint32_t tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
|
||||
uint32_t tco_en = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
|
||||
|
||||
outl(tco_sts, ACPI_BASE_ADDRESS + TCO_STS);
|
||||
return tco_sts & tco_en;
|
||||
}
|
||||
|
||||
/* Read and clear GPE status (defined in arch/acpi.h) */
|
||||
int acpi_get_gpe(int gpe)
|
||||
void soc_clear_pm_registers(uintptr_t pmc_bar)
|
||||
{
|
||||
int bank;
|
||||
uint32_t mask, sts;
|
||||
struct stopwatch sw;
|
||||
int rc = 0;
|
||||
|
||||
if (gpe < 0 || gpe > GPE0_DW3_31)
|
||||
return -1;
|
||||
|
||||
bank = gpe / 32;
|
||||
mask = 1 << (gpe % 32);
|
||||
|
||||
/* Wait up to 1ms for GPE status to clear */
|
||||
stopwatch_init_msecs_expire(&sw, 1);
|
||||
do {
|
||||
if (stopwatch_expired(&sw))
|
||||
return rc;
|
||||
|
||||
sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank));
|
||||
if (sts & mask) {
|
||||
outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank));
|
||||
rc = 1;
|
||||
}
|
||||
} while (sts & mask);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
void clear_pmc_status(void)
|
||||
{
|
||||
uint32_t prsts;
|
||||
uint32_t gen_pmcon1;
|
||||
uintptr_t pmc_bar0 = read_pmc_mmio_bar();
|
||||
|
||||
prsts = read32((void *)(pmc_bar0 + PRSTS));
|
||||
gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1));
|
||||
|
||||
gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1));
|
||||
/* Clear the status bits. The RPS field is cleared on a 0 write. */
|
||||
write32((void *)(pmc_bar0 + GEN_PMCON1), gen_pmcon1 & ~RPS);
|
||||
write32((void *)(pmc_bar0 + PRSTS), prsts);
|
||||
write32((void *)(pmc_bar + GEN_PMCON1), gen_pmcon1 & ~RPS);
|
||||
}
|
||||
|
||||
|
||||
/* Return 0, 3, or 5 to indicate the previous sleep state. */
|
||||
int chipset_prev_sleep_state(struct chipset_power_state *ps)
|
||||
void soc_get_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
|
||||
{
|
||||
/* Default to S0. */
|
||||
int prev_sleep_state = ACPI_S0;
|
||||
|
||||
if (ps->pm1_sts & WAK_STS) {
|
||||
switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
|
||||
case ACPI_S3:
|
||||
if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
|
||||
prev_sleep_state = ACPI_S3;
|
||||
break;
|
||||
case ACPI_S5:
|
||||
prev_sleep_state = ACPI_S5;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Clear SLP_TYP. */
|
||||
outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
|
||||
}
|
||||
return prev_sleep_state;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function re-writes the gpe0 register values in power state
|
||||
* cbmem variable. After system wakes from sleep state internal PMC logic
|
||||
* writes default values in GPE_CFG register which gives a wrong offset to
|
||||
* calculate the wake reason. So we need to set it again to the routing
|
||||
* table as per the devicetree.
|
||||
*/
|
||||
void fixup_power_state(void)
|
||||
{
|
||||
int i;
|
||||
struct chipset_power_state *ps;
|
||||
|
||||
ps = cbmem_find(CBMEM_ID_POWER_STATE);
|
||||
if (ps == NULL)
|
||||
return;
|
||||
|
||||
for (i = 0; i < GPE0_REG_MAX; i++) {
|
||||
ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i));
|
||||
ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i));
|
||||
printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n",
|
||||
i, ps->gpe0_sts[i], i, ps->gpe0_en[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/* returns prev_sleep_state */
|
||||
int fill_power_state(struct chipset_power_state *ps)
|
||||
{
|
||||
int i;
|
||||
uintptr_t pmc_bar0 = read_pmc_mmio_bar();
|
||||
|
||||
ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
|
||||
ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
|
||||
ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
|
||||
ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
|
||||
ps->prsts = read32((void *)(pmc_bar0 + PRSTS));
|
||||
ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1));
|
||||
ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2));
|
||||
ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3));
|
||||
|
||||
ps->prev_sleep_state = chipset_prev_sleep_state(ps);
|
||||
|
||||
printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
|
||||
ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
|
||||
printk(BIOS_DEBUG, "prsts: %08x tco_sts: %08x\n",
|
||||
ps->prsts, ps->tco_sts);
|
||||
printk(BIOS_DEBUG,
|
||||
"gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n",
|
||||
ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
|
||||
printk(BIOS_DEBUG, "smi_en: %08x smi_sts: %08x\n",
|
||||
inl(ACPI_BASE_ADDRESS + SMI_EN), inl(ACPI_BASE_ADDRESS + SMI_STS));
|
||||
for (i = 0; i < GPE0_REG_MAX; i++) {
|
||||
ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i));
|
||||
ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i));
|
||||
printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n",
|
||||
i, ps->gpe0_sts[i], i, ps->gpe0_en[i]);
|
||||
}
|
||||
printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
|
||||
return ps->prev_sleep_state;
|
||||
}
|
||||
|
||||
int vboot_platform_is_resuming(void)
|
||||
{
|
||||
if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))
|
||||
return 0;
|
||||
|
||||
return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
|
||||
}
|
||||
|
||||
/*
|
||||
* If possible, lock 0xcf9. Once the register is locked, it can't be changed.
|
||||
* This lock is reset on cold boot, hard reset, soft reset and Sx.
|
||||
*/
|
||||
void global_reset_lock(void)
|
||||
{
|
||||
uintptr_t etr = read_pmc_mmio_bar() + ETR;
|
||||
uint32_t reg;
|
||||
|
||||
reg = read32((void *)etr);
|
||||
if (reg & CF9_LOCK)
|
||||
return;
|
||||
reg |= CF9_LOCK;
|
||||
write32((void *)etr, reg);
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable or disable global reset. If global reset is enabled, hard reset and
|
||||
* soft reset will trigger global reset, where both host and TXE are reset.
|
||||
* This is cleared on cold boot, hard reset, soft reset and Sx.
|
||||
*/
|
||||
void global_reset_enable(bool enable)
|
||||
{
|
||||
uintptr_t etr = read_pmc_mmio_bar() + ETR;
|
||||
uint32_t reg;
|
||||
|
||||
reg = read32((void *)etr);
|
||||
reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST;
|
||||
write32((void *)etr, reg);
|
||||
}
|
||||
|
||||
/*
|
||||
* The PM1 control is set to S5 when vboot requests a reboot because the power
|
||||
* state code above may not have collected its data yet. Therefore, set it to
|
||||
* S5 when vboot requests a reboot. That's necessary if vboot fails in the
|
||||
* resume path and requests a reboot. This prevents a reboot loop where the
|
||||
* error is continually hit on the failing vboot resume path.
|
||||
*/
|
||||
void vboot_platform_prepare_reboot(void)
|
||||
{
|
||||
const uint16_t port = ACPI_BASE_ADDRESS + PM1_CNT;
|
||||
outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port);
|
||||
}
|
||||
|
||||
void poweroff(void)
|
||||
{
|
||||
enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
|
||||
|
||||
/*
|
||||
* Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM
|
||||
* to transition to S5 state. If halt is called in SMM, then it prevents
|
||||
* the SMI handler from being triggered and system never enters S5.
|
||||
*/
|
||||
if (!ENV_SMM)
|
||||
halt();
|
||||
}
|
||||
|
||||
void pmc_gpe_init(void)
|
||||
{
|
||||
uint32_t gpio_cfg = 0;
|
||||
uint32_t gpio_cfg_reg;
|
||||
uint8_t dw1, dw2, dw3;
|
||||
DEVTREE_CONST struct soc_intel_apollolake_config *config;
|
||||
|
||||
/* Look up the device in devicetree */
|
||||
|
|
@ -513,46 +160,27 @@ void pmc_gpe_init(void)
|
|||
}
|
||||
config = dev->chip_info;
|
||||
|
||||
uintptr_t pmc_bar = get_pmc_mmio_bar();
|
||||
/* Assign to out variable */
|
||||
*dw0 = config->gpe0_dw1;
|
||||
*dw1 = config->gpe0_dw2;
|
||||
*dw2 = config->gpe0_dw3;
|
||||
}
|
||||
|
||||
const uint32_t gpio_cfg_mask =
|
||||
(GPE0_DWX_MASK << GPE0_DW1_SHIFT) |
|
||||
(GPE0_DWX_MASK << GPE0_DW2_SHIFT) |
|
||||
(GPE0_DWX_MASK << GPE0_DW3_SHIFT);
|
||||
void soc_fill_power_state(struct chipset_power_state *ps)
|
||||
{
|
||||
uintptr_t pmc_bar0 = read_pmc_mmio_bar();
|
||||
|
||||
/* Assign to local variable */
|
||||
dw1 = config->gpe0_dw1;
|
||||
dw2 = config->gpe0_dw2;
|
||||
dw3 = config->gpe0_dw3;
|
||||
ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
|
||||
ps->prsts = read32((void *)(pmc_bar0 + PRSTS));
|
||||
ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1));
|
||||
ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2));
|
||||
ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3));
|
||||
|
||||
/* Making sure that bad values don't bleed into the other fields */
|
||||
dw1 &= GPE0_DWX_MASK;
|
||||
dw2 &= GPE0_DWX_MASK;
|
||||
dw3 &= GPE0_DWX_MASK;
|
||||
|
||||
/* Route the GPIOs to the GPE0 block. Determine that all values
|
||||
* are different, and if they aren't use the reset values.
|
||||
* DW0 is reserved/unused */
|
||||
if (dw1 == dw2 || dw2 == dw3) {
|
||||
printk(BIOS_INFO, "PMC: Using default GPE route.\n");
|
||||
gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG);
|
||||
|
||||
dw1 = (gpio_cfg >> GPE0_DW1_SHIFT) & GPE0_DWX_MASK;
|
||||
dw2 = (gpio_cfg >> GPE0_DW2_SHIFT) & GPE0_DWX_MASK;
|
||||
dw3 = (gpio_cfg >> GPE0_DW3_SHIFT) & GPE0_DWX_MASK;
|
||||
} else {
|
||||
gpio_cfg |= (uint32_t)dw1 << GPE0_DW1_SHIFT;
|
||||
gpio_cfg |= (uint32_t)dw2 << GPE0_DW2_SHIFT;
|
||||
gpio_cfg |= (uint32_t)dw3 << GPE0_DW3_SHIFT;
|
||||
}
|
||||
|
||||
gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask;
|
||||
gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask;
|
||||
|
||||
write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg);
|
||||
|
||||
/* Set the routes in the GPIO communities as well. */
|
||||
gpio_route_gpe(dw1, dw2, dw3);
|
||||
printk(BIOS_DEBUG, "prsts: %08x tco_sts: %08x\n",
|
||||
ps->prsts, ps->tco_sts);
|
||||
printk(BIOS_DEBUG,
|
||||
"gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n",
|
||||
ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
|
||||
}
|
||||
|
||||
void enable_pm_timer_emulation(void)
|
||||
|
|
@ -566,7 +194,7 @@ void enable_pm_timer_emulation(void)
|
|||
* frequency is used.
|
||||
*/
|
||||
msr.hi = (3579545ULL << 32) / CTC_FREQ;
|
||||
/* Set PM1 timer IO port and enable*/
|
||||
/* Set PM1 timer IO port and enable */
|
||||
msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR);
|
||||
wrmsr(MSR_EMULATE_PM_TMR, msr);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <fsp/util.h>
|
||||
#include <intelblocks/pmclib.h>
|
||||
#include <reset.h>
|
||||
#include <soc/heci.h>
|
||||
#include <soc/pm.h>
|
||||
|
|
@ -25,8 +26,8 @@
|
|||
|
||||
void do_global_reset(void)
|
||||
{
|
||||
global_reset_enable(1);
|
||||
do_hard_reset();
|
||||
pmc_global_reset_enable(1);
|
||||
hard_reset();
|
||||
}
|
||||
|
||||
void soc_reset_prepare(enum reset_type reset_type)
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@
|
|||
#include <fsp/util.h>
|
||||
#include <intelblocks/cpulib.h>
|
||||
#include <intelblocks/systemagent.h>
|
||||
#include <intelblocks/pmclib.h>
|
||||
#include <reset.h>
|
||||
#include <soc/cpu.h>
|
||||
#include <soc/intel/common/mrc_cache.h>
|
||||
|
|
@ -231,7 +232,7 @@ asmlinkage void car_stage_entry(void)
|
|||
|
||||
console_init();
|
||||
|
||||
s3wake = fill_power_state(ps) == ACPI_S3;
|
||||
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
|
||||
fsp_memory_init(s3wake);
|
||||
|
||||
if (punit_init())
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <intelblocks/pmclib.h>
|
||||
#include <string.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/smm.h>
|
||||
|
|
@ -30,7 +31,7 @@ void southbridge_smm_clear_state(void)
|
|||
{
|
||||
printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
|
||||
|
||||
if (get_smi_en() & APMC_EN) {
|
||||
if (pmc_get_smi_en() & APMC_EN) {
|
||||
printk(BIOS_INFO, "SMI# handler already enabled?\n");
|
||||
return;
|
||||
}
|
||||
|
|
@ -38,21 +39,21 @@ void southbridge_smm_clear_state(void)
|
|||
printk(BIOS_DEBUG, "Done\n");
|
||||
|
||||
/* Dump and clear status registers */
|
||||
clear_smi_status();
|
||||
clear_pm1_status();
|
||||
clear_tco_status();
|
||||
clear_gpe_status();
|
||||
pmc_clear_smi_status();
|
||||
pmc_clear_pm1_status();
|
||||
pmc_clear_tco_status();
|
||||
pmc_clear_gpe_status();
|
||||
}
|
||||
|
||||
void southbridge_smm_enable_smi(void)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Enabling SMIs.\n");
|
||||
/* Configure events */
|
||||
enable_pm1(PWRBTN_EN | GBL_EN);
|
||||
disable_gpe(PME_B0_EN);
|
||||
pmc_enable_pm1(PWRBTN_EN | GBL_EN);
|
||||
pmc_disable_gpe(PME_B0_EN);
|
||||
|
||||
/* Enable SMI generation */
|
||||
enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN);
|
||||
pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN);
|
||||
}
|
||||
|
||||
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
|
||||
|
|
|
|||
Loading…
Reference in New Issue