diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h
index fa59565ba8..bd42f21006 100644
--- a/src/northbridge/intel/ironlake/ironlake.h
+++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -60,6 +60,11 @@
 #define SAD_DRAM_RULE(x)	(0x80 + 4 * (x)) /* 0-7 */
 #define SAD_INTERLEAVE_LIST(x)	(0xc0 + 4 * (x)) /* 0-7 */
 
+/*
+ * QPI Link 0
+ */
+#define QPI_LINK_0		PCI_DEV(QUICKPATH_BUS, 2, 0)
+
 
 /* Device 0:2.0 PCI configuration space (Graphics Device) */
 
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index f8f6b74466..2c475694d4 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -3950,11 +3950,11 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
 		MCHBAR8_OR(0x2ca8, 1);	// guess
 	}
 
-	pci_read_config32(PCI_DEV(0xff, 2, 0), 0x048);	// !!!!
-	pci_write_config32(PCI_DEV(0xff, 2, 0), 0x048, 0x140000);
-	pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058);	// !!!!
-	pci_write_config32(PCI_DEV(0xff, 2, 0), 0x058, 0x64555);
-	pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058);	// !!!!
+	pci_read_config32(QPI_LINK_0, 0x048);	// !!!!
+	pci_write_config32(QPI_LINK_0, 0x048, 0x140000);
+	pci_read_config32(QPI_LINK_0, 0x058);	// !!!!
+	pci_write_config32(QPI_LINK_0, 0x058, 0x64555);
+	pci_read_config32(QPI_LINK_0, 0x058);	// !!!!
 	pci_read_config32(PCI_DEV (0xff, 0, 0), 0xd0);	// !!!!
 	pci_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180);
 	gav(MCHBAR32(0x1af0));	// !!!!