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asus/p3b-f,intel/i440bx: Move enable/disable_spd() call 

Change-Id: I4a324dcebcd53439206205e64c5bbb7c6eac4fb2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2020-01-07 15:17:48 +02:00
parent 7f40bd667c
commit 93e08c75d3
3 changed files with 13 additions and 4 deletions
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6
src/mainboard/asus/p3b-f/romstage.c
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@ -49,7 +49,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
* 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28 * 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28
* control which SMBus/I2C offsets can be accessed. * control which SMBus/I2C offsets can be accessed.
*/ */
static void enable_spd(void) void enable_spd(void)
{ {
outb(0x6f, PM_IO_BASE + 0x37); outb(0x6f, PM_IO_BASE + 0x37);
} }
@ -58,7 +58,7 @@ static void enable_spd(void)
* Disable SPD access after RAM init to allow access to SMBus/I2C offsets * Disable SPD access after RAM init to allow access to SMBus/I2C offsets
* 0x48/0x49/0x2d, which is required e.g. by lm-sensors. * 0x48/0x49/0x2d, which is required e.g. by lm-sensors.
*/ */
static void disable_spd(void) void disable_spd(void)
{ {
outb(0x67, PM_IO_BASE + 0x37); outb(0x67, PM_IO_BASE + 0x37);
} }
@ -71,10 +71,8 @@ void mainboard_romstage_entry(void)
enable_smbus(); enable_smbus();
enable_pm(); enable_pm();
enable_spd();
sdram_initialize(); sdram_initialize();
disable_spd();
cbmem_initialize_empty(); cbmem_initialize_empty();
} }

8
src/northbridge/intel/i440bx/raminit.c
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@ -1035,10 +1035,18 @@ void sdram_enable(void)
DUMPNORTH(); DUMPNORTH();
} }
/* Implemented under mainboard. */
void __weak enable_spd(void) { }
void __weak disable_spd(void) { }
void sdram_initialize(void) void sdram_initialize(void)
{ {
enable_spd();
dump_spd_registers(); dump_spd_registers();
sdram_set_registers(); sdram_set_registers();
sdram_set_spd_registers(); sdram_set_spd_registers();
sdram_enable(); sdram_enable();
disable_spd();
} }

3
src/northbridge/intel/i440bx/raminit.h
View File

@ -20,6 +20,9 @@
/* The 440BX supports up to four (single- or double-sided) DIMMs. */ /* The 440BX supports up to four (single- or double-sided) DIMMs. */
#define DIMM_SOCKETS 4 #define DIMM_SOCKETS 4
void enable_spd(void);
void disable_spd(void);
/* Function prototypes. */ /* Function prototypes. */
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
void sdram_set_registers(void); void sdram_set_registers(void);