soc/intel/apollolake: Add ASL methods for eMMC
Implement PS0 and PS3 methods to support eMMC power gate in S0ix suspend and resume. BUG=chrome-os-partner:53876 TEST=Suspend and Resume using 'echo freeze > /sys/power/state'. System should resume from S0ix. Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16233 Tested-by: build bot (Jenkins) Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Scope (\_SB.PCI0) {
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/* 0xD6- is the port address */
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/* 0x600- is the dynamic clock gating control register offset (GENR) */
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OperationRegion (SBMM, SystemMemory,
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Or ( Or (CONFIG_IOSF_BASE_ADDRESS,
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ShiftLeft(0xD6, 16)), 0x0600), 0x18)
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Field (SBMM, DWordAcc, NoLock, Preserve)
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{
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GENR, 32,
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}
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/* SCC power gate control method, this method must be serialized as
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* multiple device will control the GENR register
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*
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* Arguments: (2)
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* Arg0: 0-AND 1-OR
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* Arg1: Value
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*/
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Method (SCPG, 2, Serialized)
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{
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if (LEqual(Arg0, 0x1)) {
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Or (^GENR, Arg1, ^GENR)
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} ElseIf (LEqual(Arg0, 0x0)){
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And (^GENR, Arg1, ^GENR)
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}
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}
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/* eMMC */
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Device (SDHA) {
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Name (_ADR, 0x001C0000)
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Name (_DDN, "Intel(R) eMMC Controller - 80865ACC")
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Method (_PS0, 0, NotSerialized)
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{
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/* Clear clock gate
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* Clear bit 6 and 0
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*/
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^^SCPG(0,0xFFFFFFBE)
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/* Sleep 2 ms */
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Sleep (2)
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}
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Method (_PS3, 0, NotSerialized)
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{
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/* Enable power gate
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* Restore clock gate
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* Restore bit 6 and 0
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*/
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^^SCPG(1,0x00000041)
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}
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} /* Device (SDHA) */
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}
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@ -31,5 +31,8 @@
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/* LPC */
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#include "lpc.asl"
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/* eMMC */
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#include "scs.asl"
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/* PCI _OSC */
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#include <soc/intel/common/acpi/pci_osc.asl>
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