soc/intel/alderlake: Add support for ADL-N CPU Type
Add Alder Lake-N case for adl_cpu_type and get_supported_lpm_mask. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: If2917ac356fd80f84bcaf70ed710d329e77f7a6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
This commit is contained in:
parent
dc35d2a693
commit
93f50b35a4
|
@ -168,6 +168,11 @@ enum adl_cpu_type get_adl_cpu_type(void)
|
|||
PCI_DEVICE_ID_INTEL_ADL_S_ID_15,
|
||||
};
|
||||
|
||||
const uint16_t adl_n_mch_ids[] = {
|
||||
PCI_DEVICE_ID_INTEL_ADL_N_ID_1,
|
||||
PCI_DEVICE_ID_INTEL_ADL_N_ID_2,
|
||||
};
|
||||
|
||||
const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT),
|
||||
PCI_FUNC(SA_DEVFN_ROOT)),
|
||||
PCI_DEVICE_ID);
|
||||
|
@ -187,6 +192,11 @@ enum adl_cpu_type get_adl_cpu_type(void)
|
|||
return ADL_S;
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < ARRAY_SIZE(adl_n_mch_ids); i++) {
|
||||
if (adl_n_mch_ids[i] == mchid)
|
||||
return ADL_N;
|
||||
}
|
||||
|
||||
return ADL_UNKNOWN;
|
||||
}
|
||||
|
||||
|
@ -195,6 +205,7 @@ uint8_t get_supported_lpm_mask(void)
|
|||
enum adl_cpu_type type = get_adl_cpu_type();
|
||||
switch (type) {
|
||||
case ADL_M: /* fallthrough */
|
||||
case ADL_N:
|
||||
case ADL_P:
|
||||
return LPM_S0i2_0 | LPM_S0i3_0;
|
||||
case ADL_S:
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
enum adl_cpu_type {
|
||||
ADL_UNKNOWN,
|
||||
ADL_M,
|
||||
ADL_N,
|
||||
ADL_P,
|
||||
ADL_S,
|
||||
};
|
||||
|
|
Loading…
Reference in New Issue