soc/intel/alderlake: Add support for ADL-N CPU Type
Add Alder Lake-N case for adl_cpu_type and get_supported_lpm_mask. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: If2917ac356fd80f84bcaf70ed710d329e77f7a6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
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@ -168,6 +168,11 @@ enum adl_cpu_type get_adl_cpu_type(void)
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PCI_DEVICE_ID_INTEL_ADL_S_ID_15,
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PCI_DEVICE_ID_INTEL_ADL_S_ID_15,
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};
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};
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const uint16_t adl_n_mch_ids[] = {
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PCI_DEVICE_ID_INTEL_ADL_N_ID_1,
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PCI_DEVICE_ID_INTEL_ADL_N_ID_2,
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};
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const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT),
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const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT),
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PCI_FUNC(SA_DEVFN_ROOT)),
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PCI_FUNC(SA_DEVFN_ROOT)),
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PCI_DEVICE_ID);
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PCI_DEVICE_ID);
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@ -187,6 +192,11 @@ enum adl_cpu_type get_adl_cpu_type(void)
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return ADL_S;
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return ADL_S;
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}
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}
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for (size_t i = 0; i < ARRAY_SIZE(adl_n_mch_ids); i++) {
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if (adl_n_mch_ids[i] == mchid)
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return ADL_N;
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}
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return ADL_UNKNOWN;
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return ADL_UNKNOWN;
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}
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}
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@ -195,6 +205,7 @@ uint8_t get_supported_lpm_mask(void)
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enum adl_cpu_type type = get_adl_cpu_type();
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enum adl_cpu_type type = get_adl_cpu_type();
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switch (type) {
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switch (type) {
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case ADL_M: /* fallthrough */
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case ADL_M: /* fallthrough */
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case ADL_N:
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case ADL_P:
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case ADL_P:
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return LPM_S0i2_0 | LPM_S0i3_0;
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return LPM_S0i2_0 | LPM_S0i3_0;
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case ADL_S:
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case ADL_S:
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@ -22,6 +22,7 @@
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enum adl_cpu_type {
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enum adl_cpu_type {
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ADL_UNKNOWN,
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ADL_UNKNOWN,
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ADL_M,
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ADL_M,
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ADL_N,
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ADL_P,
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ADL_P,
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ADL_S,
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ADL_S,
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};
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};
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