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soc/intel/xeon/spr: Enforce POR frequency setting 

For RMT build, add kconfig option to enforce Plan Of Record
restriction on DDR5 frequency & voltage settings.

Change-Id: Ibfcaaf47fec3bd5d8a858309918b3af2f8d976e9
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This commit is contained in:
Naresh Solanki 2023-10-06 14:35:58 +02:00 committed by Shelley Chen
parent 8ed0cd0acc
commit 93ffdee5ed
2 changed files with 10 additions and 1 deletions
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8
src/soc/intel/xeon_sp/spr/Kconfig
View File

@ -187,4 +187,12 @@ config ENABLE_RMT
help
Enable Rank Margining Tool. This option is intended for debugging and
validation and should normally be disabled.
config RMT_MEM_POR_FREQ
bool "Enforce Plan Of Record restrictions for DDR5 frequency and voltage"
default n
depends on ENABLE_RMT
help
When RMT is enabled. Select this option to enforce Intel Plan Of Record(POR)
restriction on DDR5 frequency & voltage settings.
endif

3
src/soc/intel/xeon_sp/spr/romstage.c
View File

@ -279,7 +279,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mupd->FspmConfig.serialDebugMsgLvl = 0x3;
mupd->FspmConfig.AllowedSocketsInParallel = 0x1;
mupd->FspmConfig.EnforcePopulationPor = 0x1;
mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0;
if (CONFIG(RMT_MEM_POR_FREQ))
mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0;
}
/* SPR-FSP has no UPD to disable HDA, so do it manually here... */