mediatek/mt8183: Use different DRAM frequencies for eMCP DDR
Devices using eMCP may run at a high DRAM frequency (e.g., 3600Mbps) while those with discrete DRAM can only run at 3200Mbps. This patch enables 3600Mbps for eMCP DDR for better system performance. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test passes on Kukui Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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@ -19,9 +19,17 @@
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#include <soc/dramc_pi_api.h>
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#include <soc/dramc_register.h>
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#define LP4X_HIGH_FREQ LP4X_DDR3200
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#define LP4X_MIDDLE_FREQ LP4X_DDR2400
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#define LP4X_LOW_FREQ LP4X_DDR1600
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static const u8 freq_shuffle[DRAM_DFS_SHUFFLE_MAX] = {
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[DRAM_DFS_SHUFFLE_1] = LP4X_DDR3200,
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[DRAM_DFS_SHUFFLE_2] = LP4X_DDR2400,
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[DRAM_DFS_SHUFFLE_3] = LP4X_DDR1600,
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};
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static const u8 freq_shuffle_emcp[DRAM_DFS_SHUFFLE_MAX] = {
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[DRAM_DFS_SHUFFLE_1] = LP4X_DDR3600,
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[DRAM_DFS_SHUFFLE_2] = LP4X_DDR3200,
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[DRAM_DFS_SHUFFLE_3] = LP4X_DDR1600,
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};
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u32 frequency_table[LP4X_DDRFREQ_MAX] = {
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[LP4X_DDR1600] = 1600,
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@ -349,9 +357,16 @@ static void after_calib(void)
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void mt_set_emi(const struct sdram_params *params)
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{
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u32 current_freq = LP4X_HIGH_FREQ;
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const u8 *freq_tbl;
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u8 current_freqsel;
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init_dram(params, current_freq);
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do_calib(params, current_freq);
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if (CONFIG(MT8183_DRAM_EMCP))
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freq_tbl = freq_shuffle_emcp;
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else
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freq_tbl = freq_shuffle;
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current_freqsel = freq_tbl[DRAM_DFS_SHUFFLE_1];
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init_dram(params, current_freqsel);
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do_calib(params, current_freqsel);
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after_calib();
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}
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@ -16,7 +16,12 @@
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#ifndef _DRAMC_COMMON_MT8183_H_
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#define _DRAMC_COMMON_MT8183_H_
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#define DRAM_DFS_SHUFFLE_MAX 3
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enum {
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DRAM_DFS_SHUFFLE_1 = 0,
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DRAM_DFS_SHUFFLE_2,
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DRAM_DFS_SHUFFLE_3,
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DRAM_DFS_SHUFFLE_MAX
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};
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enum {
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CHANNEL_A = 0,
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