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mediatek/mt8183: Use different DRAM frequencies for eMCP DDR 

Devices using eMCP may run at a high DRAM frequency (e.g., 3600Mbps)
while those with discrete DRAM can only run at 3200Mbps. This patch
enables 3600Mbps for eMCP DDR for better system performance.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly and stress test passes on Kukui

Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Huayang Duan 2019-08-19 16:40:01 +08:00 committed by Patrick Georgi
parent 1011ed76a6
commit 9400f84d31
2 changed files with 27 additions and 7 deletions
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27
src/soc/mediatek/mt8183/emi.c
View File

@ -19,9 +19,17 @@
#include <soc/dramc_pi_api.h> #include <soc/dramc_pi_api.h>
#include <soc/dramc_register.h> #include <soc/dramc_register.h>
#define LP4X_HIGH_FREQ LP4X_DDR3200 static const u8 freq_shuffle[DRAM_DFS_SHUFFLE_MAX] = {
#define LP4X_MIDDLE_FREQ LP4X_DDR2400 [DRAM_DFS_SHUFFLE_1] = LP4X_DDR3200,
#define LP4X_LOW_FREQ LP4X_DDR1600 [DRAM_DFS_SHUFFLE_2] = LP4X_DDR2400,
[DRAM_DFS_SHUFFLE_3] = LP4X_DDR1600,
};
static const u8 freq_shuffle_emcp[DRAM_DFS_SHUFFLE_MAX] = {
[DRAM_DFS_SHUFFLE_1] = LP4X_DDR3600,
[DRAM_DFS_SHUFFLE_2] = LP4X_DDR3200,
[DRAM_DFS_SHUFFLE_3] = LP4X_DDR1600,
};
u32 frequency_table[LP4X_DDRFREQ_MAX] = { u32 frequency_table[LP4X_DDRFREQ_MAX] = {
[LP4X_DDR1600] = 1600, [LP4X_DDR1600] = 1600,
@ -349,9 +357,16 @@ static void after_calib(void)
void mt_set_emi(const struct sdram_params *params) void mt_set_emi(const struct sdram_params *params)
{ {
u32 current_freq = LP4X_HIGH_FREQ; const u8 *freq_tbl;
u8 current_freqsel;
init_dram(params, current_freq); if (CONFIG(MT8183_DRAM_EMCP))
do_calib(params, current_freq); freq_tbl = freq_shuffle_emcp;
else
freq_tbl = freq_shuffle;
current_freqsel = freq_tbl[DRAM_DFS_SHUFFLE_1];
init_dram(params, current_freqsel);
do_calib(params, current_freqsel);
after_calib(); after_calib();
} }

7
src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h
View File

@ -16,7 +16,12 @@
#ifndef _DRAMC_COMMON_MT8183_H_ #ifndef _DRAMC_COMMON_MT8183_H_
#define _DRAMC_COMMON_MT8183_H_ #define _DRAMC_COMMON_MT8183_H_
#define DRAM_DFS_SHUFFLE_MAX 3 enum {
DRAM_DFS_SHUFFLE_1 = 0,
DRAM_DFS_SHUFFLE_2,
DRAM_DFS_SHUFFLE_3,
DRAM_DFS_SHUFFLE_MAX
};
enum { enum {
CHANNEL_A = 0, CHANNEL_A = 0,