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mb/gigabyte/ga-{h61m-s2pv,b75m-d3h,b75m-d3v}: Clean up mainboard code 

I ported ga-h61m-s2pv based on the two Gigabyte b75m boards.
Based on another mainboard's code review comments, this patch
improves the code quality of these three similar boards.

ga-h61m-s2pv is tested and confirmed to be working, but I cannot
say the same regarding the other two mainboards as I do not have them.

Change-Id: Ib7747cceb5ba56f791677204cdc4c54c129c70c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2018-06-24 12:02:59 +02:00 committed by Nico Huber
parent dfc30130e9
commit 940bb4ea42
17 changed files with 103 additions and 268 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl
View File

@ -1 +0,0 @@
// Blank

3
src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
View File

@ -35,8 +35,5 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
// the lid is open by default.
gnvs->lids = 1;
acpi_update_thermal_table(gnvs);
}

2
src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
View File

@ -1,7 +1,7 @@
chip northbridge/intel/sandybridge
# IGD Displays
register "gfx.ndid" = "3"
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
device cpu_cluster 0 on
chip cpu/intel/socket_LGA1155

7
src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
View File

@ -25,16 +25,15 @@ DefinitionBlock(
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
/* global NVS and variables. */
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
}

3
src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c
View File

@ -14,8 +14,9 @@
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* FIXME: Add configuration for sound */
};
const u32 pc_beep_verbs[0] = {};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;

17
src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
View File

@ -15,22 +15,9 @@
* GNU General Public License for more details.
*/
#include <types.h>
#include <string.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <drivers/intel/gma/int15.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <smbios.h>
#include <device/pci.h>
#include <cbfs.h>
static void mainboard_init(struct device *dev)
{
@ -75,7 +62,9 @@ static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0);
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
GMA_INT15_PANEL_FIT_DEFAULT,
GMA_INT15_BOOT_DISPLAY_CRT, 0);
}
struct chip_operations mainboard_ops = {

187
src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
View File

@ -13,42 +13,50 @@
* GNU General Public License for more details.
*/
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8728f/it8728f.h>
#define SUPERIO_BASE 0x2e
#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0)
#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
#define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <console/console.h>
#include <superio/ite/it8728f/it8728f.h>
#include <superio/ite/common/ite.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
static void it8728f_b75md3h_disable_reboot(pnp_devfn_t dev)
void mainboard_rcba_config(void)
{
/* GPIO SIO settings */
ite_reg_write(dev, 0xEF, 0x7E); // magic
/* Enable HECI */
RCBA32(FD2) &= ~0x2;
}
ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16
ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34
ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port
ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00
ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear!
ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear!
ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in
ite_reg_write(dev, 0xe9, 0x27); // bus select disable
ite_reg_write(dev, 0xf0, 0x10); // ?
ite_reg_write(dev, 0xf1, 0x42); // ?
ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12)
void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
/* Initialize SuperIO */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_reg_write(SIO_GPIO, 0xEF, 0x7E); // magic SIO disable reboot
/* FIXME: These values could be configured in ramstage */
ite_reg_write(SIO_GPIO, 0x25, 0x40); // gpio pin function -> gp16
ite_reg_write(SIO_GPIO, 0x27, 0x10); // gpio pin function -> gp34
ite_reg_write(SIO_GPIO, 0x2c, 0x80); // smbus isolation on parallel port
ite_reg_write(SIO_GPIO, 0x62, 0x0a); // simple iobase 0xa00
ite_reg_write(SIO_GPIO, 0x72, 0x20); // watchdog timeout clear!
ite_reg_write(SIO_GPIO, 0x73, 0x00); // watchdog timeout clear!
ite_reg_write(SIO_GPIO, 0xcb, 0x00); // simple io set4 direction -> in
ite_reg_write(SIO_GPIO, 0xe9, 0x27); // bus select disable
ite_reg_write(SIO_GPIO, 0xf0, 0x10); // ?
ite_reg_write(SIO_GPIO, 0xf1, 0x42); // ?
ite_reg_write(SIO_GPIO, 0xf6, 0x1c); // hwmon alert beep -> gp36(pin12)
/* EC SIO settings */
ite_reg_write(IT8728F_EC, 0xf1, 0xc0);
@ -61,102 +69,6 @@ static void it8728f_b75md3h_disable_reboot(pnp_devfn_t dev)
ite_reg_write(IT8728F_EC, 0x30, 0x01);
}
void mainboard_rcba_config(void)
{
/*
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80);
outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
RCBA32(0x3500) = 0x2000035f;
RCBA32(0x3504) = 0x2000035f;
RCBA32(0x3508) = 0x2000035f;
RCBA32(0x350c) = 0x2000035f;
RCBA32(0x3510) = 0x2000035f;
RCBA32(0x3514) = 0x2000035f;
RCBA32(0x3518) = 0x2000035f;
RCBA32(0x351c) = 0x2000035f;
RCBA32(0x3520) = 0x2000035f;
RCBA32(0x3524) = 0x2000035f;
RCBA32(0x3528) = 0x2000035f;
RCBA32(0x352c) = 0x2000035f;
RCBA32(0x3530) = 0x2000035f;
RCBA32(0x3534) = 0x2000035f;
RCBA32(0x3560) = 0x024c8001;
RCBA32(0x3564) = 0x000024a3;
RCBA32(0x3568) = 0x00040002;
RCBA32(0x356c) = 0x01000050;
RCBA32(0x3570) = 0x02000662;
RCBA32(0x3574) = 0x18000f9f;
RCBA32(0x3578) = 0x1800ff4f;
RCBA32(0x357c) = 0x0001d530;
RCBA32(0x35a0) = 0xc0300c03;
RCBA32(0x35a4) = 0x00241803;
pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
outw (0x0000, DEFAULT_PMBASE | 0x003c);
RCBA32(0x2240) = 0x00330e71;
RCBA32(0x2244) = 0x003f0eb1;
RCBA32(0x2248) = 0x002102cd;
RCBA32(0x224c) = 0x00f60000;
RCBA32(0x2250) = 0x00020000;
RCBA32(0x2254) = 0x00e3004c;
RCBA32(0x2258) = 0x00e20bef;
RCBA32(0x2260) = 0x003304ed;
RCBA32(0x2278) = 0x001107c1;
RCBA32(0x227c) = 0x001d07e9;
RCBA32(0x2280) = 0x00e20000;
RCBA32(0x2284) = 0x00ee0000;
RCBA32(0x2288) = 0x005b05d3;
RCBA32(0x2318) = 0x04b8ff2e;
RCBA32(0x231c) = 0x03930f2e;
// RCBA32(0x3418) = 0x1fee1fe1;
RCBA32(0x3808) = 0x005044a3;
RCBA32(0x3810) = 0x52410000;
RCBA32(0x3814) = 0x0000008a;
RCBA32(0x3818) = 0x00000006;
RCBA32(0x381c) = 0x0000072e;
RCBA32(0x3820) = 0x0000000a;
RCBA32(0x3824) = 0x00000123;
RCBA32(0x3828) = 0x00000009;
RCBA32(0x382c) = 0x00000001;
RCBA32(0x3834) = 0x0000061a;
RCBA32(0x3838) = 0x00000003;
RCBA32(0x383c) = 0x00000a76;
RCBA32(0x3840) = 0x00000004;
RCBA32(0x3844) = 0x0000e5e4;
RCBA32(0x3848) = 0x0000000e;
*/
/* Enable HECI */
RCBA32(FD2) &= ~0x2;
}
void pch_enable_lpc(void)
{
/*
* Enable:
* EC Decode Range PortA30/A20
* SuperIO Port2E/2F
* PS/2 Keyboard/Mouse Port60/64
* FDD Port3F0h-3F5h and Port3F7h
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
/* Initialize SuperIO */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8728f_b75md3h_disable_reboot(SUPERIO_GPIO);
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 5, 0 },
{ 1, 5, 0 },
@ -181,29 +93,8 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) {
read_spd (&spd[3], 0x53, id_only);
}
#if 0
static void dmi_config(void)
void mainboard_early_init(int s3resume)
{
DMIBAR32(0x0218) = 0x06aa0b0c;
DMIBAR32(0x021c) = 0x0b0d0b0d;
DMIBAR32(0x0300) = 0x0011028d;
DMIBAR32(0x0304) = 0x002102cd;
DMIBAR32(0x030c) = 0x007d004b;
DMIBAR32(0x0310) = 0x007e004c;
DMIBAR32(0x0318) = 0x002304ad;
DMIBAR32(0x031c) = 0x003304ed;
DMIBAR32(0x03b8) = 0x005c05a4;
DMIBAR32(0x03bc) = 0x006c05e4;
DMIBAR32(0x0530) = 0x41d3b000;
DMIBAR32(0x0534) = 0x00019f80;
DMIBAR32(0x0ba4) = 0x0000000d;
DMIBAR32(0x0d80) = 0x1c9cfc0b;
DMIBAR32(0x0e1c) = 0x20000000;
DMIBAR32(0x0e2c) = 0x20000000;
}
#endif
void mainboard_early_init(int s3resume) {
}
void mainboard_config_superio(void)

1
src/mainboard/gigabyte/ga-b75m-d3v/acpi/video.asl
View File

@ -1 +0,0 @@
// Blank

3
src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
View File

@ -35,8 +35,5 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
// the lid is open by default.
gnvs->lids = 1;
acpi_update_thermal_table(gnvs);
}

2
src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb
View File

@ -1,6 +1,6 @@
chip northbridge/intel/sandybridge
register "gfx.ndid" = "3"
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
device cpu_cluster 0 on
chip cpu/intel/socket_LGA1155

7
src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
View File

@ -25,16 +25,15 @@ DefinitionBlock(
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
/* global NVS and variables. */
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
}

4
src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c
View File

@ -36,6 +36,6 @@ const u32 cim_verb_data[] = {
AZALIA_PIN_CFG(0, 0x1f, 0x411111f0)
};
const u32 pc_beep_verbs[] = {
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;

17
src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
View File

@ -15,22 +15,9 @@
* GNU General Public License for more details.
*/
#include <types.h>
#include <string.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <drivers/intel/gma/int15.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <smbios.h>
#include <device/pci.h>
#include <cbfs.h>
static void mainboard_init(struct device *dev)
{
@ -75,7 +62,9 @@ static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0);
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
GMA_INT15_PANEL_FIT_DEFAULT,
GMA_INT15_BOOT_DISPLAY_CRT, 0);
}
struct chip_operations mainboard_ops = {

97
src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
View File

@ -13,42 +13,50 @@
* GNU General Public License for more details.
*/
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8728f/it8728f.h>
#define SUPERIO_BASE 0x2e
#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0)
#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
#define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <console/console.h>
#include <superio/ite/it8728f/it8728f.h>
#include <superio/ite/common/ite.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
static void it8728f_b75md3v_disable_reboot(pnp_devfn_t dev)
void mainboard_rcba_config(void)
{
/* GPIO SIO settings */
ite_reg_write(dev, 0xEF, 0x7E); // magic
/* Enable HECI */
RCBA32(FD2) &= ~0x2;
}
ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16
ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34
ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port
ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00
ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear!
ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear!
ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in
ite_reg_write(dev, 0xe9, 0x27); // bus select disable
ite_reg_write(dev, 0xf0, 0x10); // ?
ite_reg_write(dev, 0xf1, 0x42); // ?
ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12)
void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
/* Initialize SuperIO */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_reg_write(SIO_GPIO, 0xEF, 0x7E); // magic SIO disable reboot
/* FIXME: These values could be configured in ramstage */
ite_reg_write(SIO_GPIO, 0x25, 0x40); // gpio pin function -> gp16
ite_reg_write(SIO_GPIO, 0x27, 0x10); // gpio pin function -> gp34
ite_reg_write(SIO_GPIO, 0x2c, 0x80); // smbus isolation on parallel port
ite_reg_write(SIO_GPIO, 0x62, 0x0a); // simple iobase 0xa00
ite_reg_write(SIO_GPIO, 0x72, 0x20); // watchdog timeout clear!
ite_reg_write(SIO_GPIO, 0x73, 0x00); // watchdog timeout clear!
ite_reg_write(SIO_GPIO, 0xcb, 0x00); // simple io set4 direction -> in
ite_reg_write(SIO_GPIO, 0xe9, 0x27); // bus select disable
ite_reg_write(SIO_GPIO, 0xf0, 0x10); // ?
ite_reg_write(SIO_GPIO, 0xf1, 0x42); // ?
ite_reg_write(SIO_GPIO, 0xf6, 0x1c); // hwmon alert beep -> gp36(pin12)
/* EC SIO settings */
ite_reg_write(IT8728F_EC, 0xf1, 0xc0);
@ -61,34 +69,6 @@ static void it8728f_b75md3v_disable_reboot(pnp_devfn_t dev)
ite_reg_write(IT8728F_EC, 0x30, 0x01);
}
void mainboard_rcba_config(void)
{
/* Enable HECI */
RCBA32(FD2) &= ~0x2;
}
void pch_enable_lpc(void)
{
/*
* Enable:
* EC Decode Range PortA30/A20
* SuperIO Port2E/2F
* PS/2 Keyboard/Mouse Port60/64
* FDD Port3F0h-3F5h and Port3F7h
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
/* Initialize SuperIO */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8728f_b75md3v_disable_reboot(SUPERIO_GPIO);
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 5, 0 },
{ 1, 5, 0 },
@ -106,6 +86,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 5, 6 },
};
/* FIXME: This board only has two DIMM slots! */
void mainboard_get_spd(spd_raw_data *spd, bool id_only) {
read_spd (&spd[0], 0x50, id_only);
read_spd (&spd[1], 0x51, id_only);

8
src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb
View File

@ -14,14 +14,8 @@
##
chip northbridge/intel/sandybridge
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
register "gfx.link_frequency_270_mhz" = "0"
register "gfx.ndid" = "3"
register "gfx.use_spread_spectrum_clock" = "0"
register "gpu_dp_b_hotplug" = "4"
register "gpu_dp_c_hotplug" = "4"
register "gpu_dp_d_hotplug" = "4"
register "gpu_panel_port_select" = "0"
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
device cpu_cluster 0x0 on
chip cpu/intel/socket_LGA1155
device lapic 0x0 on

6
src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl
View File

@ -38,9 +38,9 @@ DefinitionBlock(
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
}
}
}

6
src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
View File

@ -57,11 +57,11 @@ void mainboard_early_init(int s3resume)
void mainboard_config_superio(void)
{
/* Enable serial port and flip some magic bits */
/* Enable serial port */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E); // magic
/* Disable SIO WDT which kicks in DualBIOS */
ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E);
}
void mainboard_get_spd(spd_raw_data *spd, bool id_only)