mb/google/drallion: modify PCIE setting
Based on HW schematic to modify PCIE setting. BUG=b:138082886 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia744a6f3cba76c507c1c43b0a981cb6d89c1a40f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
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@ -189,22 +189,27 @@ chip soc/intel/cannonlake
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},
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}"
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# PCIe port 9 for Card Reader
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[4]" = "8"
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register "PcieClkSrcClkReq[4]" = "4"
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# PCIe port 10 for M.2 2230 WLAN
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register "PcieRpEnable[9]" = "1"
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register "PcieClkSrcUsage[2]" = "9"
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register "PcieClkSrcClkReq[2]" = "2"
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# PCIe port 11 for card reader
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register "PcieRpEnable[10]" = "1"
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register "PcieRpLtrEnable[10]" = "1"
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register "PcieClkSrcUsage[1]" = "10"
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register "PcieClkSrcUsage[1]" = "9"
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register "PcieClkSrcClkReq[1]" = "1"
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# PCIe port 12 for M.2 3042 WWAN
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register "PcieRpEnable[11]" = "1"
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register "PcieClkSrcUsage[0]" = "11"
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register "PcieClkSrcClkReq[0]" = "0"
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# PCIe port 13 for M.2 2280 SSD
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register "PcieRpEnable[12]" = "1"
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register "PcieRpLtrEnable[12]" = "1"
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register "PcieClkSrcUsage[4]" = "12"
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register "PcieClkSrcClkReq[4]" = "4"
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register "PcieClkSrcUsage[2]" = "12"
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register "PcieClkSrcClkReq[2]" = "2"
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# GPIO PM programming
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register "gpio_override_pm" = "1"
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@ -359,7 +364,7 @@ chip soc/intel/cannonlake
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end
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end # I2C #4
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device pci 19.1 off end # I2C #5
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device pci 19.2 off end # UART #2
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device pci 19.2 on end # UART #2
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device pci 1a.0 off end # eMMC
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device pci 1c.0 off end # PCI Express Port 1 (USB)
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device pci 1c.1 off end # PCI Express Port 2 (USB)
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@ -373,12 +378,12 @@ chip soc/intel/cannonlake
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smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
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end # PCI Express Port 9
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device pci 1d.1 on end # PCI Express Port 10
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device pci 1d.2 on end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 on end # PCI Express Port 12
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device pci 1d.4 on
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
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end # PCI Express Port 13 (x4)
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device pci 1e.0 on end # UART #0
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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