diff --git a/src/drivers/pc80/tpm/tpm.c b/src/drivers/pc80/tpm/tpm.c index 012f61dbed..22dbc41144 100644 --- a/src/drivers/pc80/tpm/tpm.c +++ b/src/drivers/pc80/tpm/tpm.c @@ -52,10 +52,6 @@ TPM_DEBUG("Write reg 0x%x with 0x%x\n", (reg_), (val_)) #define printf(x...) printk(BIOS_ERR, x) -#define readb(_a) (*(volatile unsigned char *) (_a)) -#define writeb(_v, _a) (*(volatile unsigned char *) (_a) = (_v)) -#define readl(_a) (*(volatile unsigned long *) (_a)) -#define writel(_v, _a) (*(volatile unsigned long *) (_a) = (_v)) /* coreboot wrapper for TPM driver (end) */ #ifndef CONFIG_TPM_TIS_BASE_ADDRESS diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c index 4a069fa02e..0df16e2a7b 100644 --- a/src/soc/nvidia/tegra/usb.c +++ b/src/soc/nvidia/tegra/usb.c @@ -158,26 +158,60 @@ void usb_setup_utmip(void *usb_base) /* Take stuff out of pwrdn and add some magic numbers from U-Boot */ write32(&usb->utmip.xcvr0, - 0x8 << 25 | 0x3 << 22 | 0 << 21 | 0 << 18 | 0 << 16 | 0 << 14 | 1 << 13 | 0x1 << 10 | 0x1 << 8 | 0x4 << 0 | 0); - write32(&usb->utmip.xcvr1, 0x7 << 18 | 0 << 4 | 0 << 2 | 0 << 0 | 0); - write32(&usb->utmip.tx, 1 << 19 | 1 << 16 | 1 << 9 | 0); + 0x8 << 25 | /* HS slew rate [10:4] */ + 0x3 << 22 | /* HS driver output 'SETUP' [6:4] */ + 0 << 21 | /* LS bias selection */ + 0 << 18 | /* PDZI pwrdn */ + 0 << 16 | /* PD2 pwrdn */ + 0 << 14 | /* PD pwrdn */ + 1 << 13 | /* (rst) HS receiver terminations */ + 0x1 << 10 | /* (rst) LS falling slew rate */ + 0x1 << 8 | /* (rst) LS rising slew rate */ + 0x4 << 0); /* HS driver output 'SETUP' [3:0] */ + write32(&usb->utmip.xcvr1, + 0x7 << 18 | /* Termination range adjustment */ + 0 << 4 | /* PDDR pwrdn */ + 0 << 2 | /* PDCHRP pwrdn */ + 0 << 0); /* PDDISC pwrdn */ + write32(&usb->utmip.tx, + 1 << 19 | /* FS send initial J before sync(?) */ + 1 << 16 | /* (rst) Allow stuff error on SoP */ + 1 << 9); /* (rst) Check disc only on EoP */ write32(&usb->utmip.hsrx0, - 0x2 << 30 | 1 << 28 | 0x1 << 24 | 0x3 << 21 | 0x11 << 15 | 0x10 << 10 | 0); + 0x2 << 30 | /* (rst) Keep pattern on active */ + 1 << 28 | /* (rst) Realign inertia on pkt */ + 0x1 << 24 | /* (rst) edges-1 to move sampling */ + 0x3 << 21 | /* (rst) squelch delay on EoP */ + 0x11 << 15 | /* cycles until IDLE */ + 0x10 << 10); /* elastic input depth */ /* U-Boot claims the USBD values for these are used across all UTMI+ * PHYs. That sounds so horribly wrong that I'm not going to implement * it, but keep it in mind if we're ever not using the USBD port. */ write32(&usb->utmip.bias0, - 0x1 << 24 | 1 << 23 | 1 << 22 | 1 << 11 | 0 << 10 | 0x1 << 2 | 0x2 << 0 | 0); + 0x1 << 24 | /* HS disconnect detect level [2] */ + 1 << 23 | /* (rst) IDPD value */ + 1 << 22 | /* (rst) IDPD select */ + 1 << 11 | /* (rst) OTG pwrdn */ + 0 << 10 | /* bias pwrdn */ + 0x1 << 2 | /* HS disconnect detect level [1:0] */ + 0x2 << 0); /* HS squelch detect level */ - write32(&usb->utmip.bias1, khz / 2200 << 3 | 1 << 2 | 0 << 0 | 0); + write32(&usb->utmip.bias1, + khz / 2200 << 3 | /* bias pwrdn cycles (20us?) */ + 1 << 2 | /* (rst) VBUS wakeup pwrdn */ + 0 << 0); /* PDTRK pwrdn */ - write32(&usb->utmip.debounce, 0xffff << 16 | 25 * khz / 10 << 0 | 0); + write32(&usb->utmip.debounce, + 0xffff << 16 | /* (rst) */ + 25 * khz / 10 << 0); /* TODO: what's this, really? */ udelay(1); setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ - write32(&usb->suspend_ctrl, 1 << 12 | 0 << 11 | 0); + write32(&usb->suspend_ctrl, + 1 << 12 | /* UTMI+ enable */ + 0 << 11); /* UTMI+ reset */ usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP); printk(BIOS_DEBUG, "USB controller @ %p set up with UTMI+ PHY\n",usb_base); diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 1d124b220f..8009b48080 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -243,14 +243,25 @@ static void init_utmip_pll(void) clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ udelay(1); - write32(&clk_rst->utmip_pll_cfg0, 80 << 16 | 1 << 8 | 0); /* 960MHz * 1 / 80 == 12 MHz */ + write32(&clk_rst->utmip_pll_cfg0, /* 960MHz * 1 / 80 == 12 MHz */ + 80 << 16 | /* (rst) phy_divn */ + 1 << 8); /* (rst) phy_divm */ write32(&clk_rst->utmip_pll_cfg1, - CEIL_DIV(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | CEIL_DIV(khz, 102) << 0 | 0); + CEIL_DIV(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */ + 0 << 16 | /* PLLU pwrdn */ + 0 << 14 | /* pll_enable pwrdn */ + 0 << 12 | /* pll_active pwrdn */ + CEIL_DIV(khz, 102) << 0); /* phy_stbl_cnt / 256 (2.5ms) */ /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */ write32(&clk_rst->utmip_pll_cfg2, - 0 << 24 | CEIL_DIV(khz, 3200) << 18 | CEIL_DIV(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0); + 0 << 24 | /* SAMP_D/XDEV pwrdn */ + CEIL_DIV(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */ + CEIL_DIV(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */ + 0 << 4 | /* SAMP_C/USB3 pwrdn */ + 0 << 2 | /* SAMP_B/XHOST pwrdn */ + 0 << 0); /* SAMP_A/USBD pwrdn */ setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ } @@ -387,8 +398,8 @@ clock_display(u32 frequency) * been determined through trial and error (must lead to div 13 at 24MHz). */ void clock_early_uart(void) { - write32(&clk_rst->clk_src_uarta, - CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900)); + write32(&clk_rst->clk_src_uarta, CLK_M << CLK_SOURCE_SHIFT | + CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900)); setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA); udelay(2); clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA); @@ -484,7 +495,11 @@ void clock_cpu0_config(void *entry) // Set up cclk_brst and divider. write32(&clk_rst->cclk_brst_pol, - (CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28)); + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | + (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28)); write32(&clk_rst->super_cclk_div, CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB); @@ -506,20 +521,31 @@ void clock_cpu0_remove_reset(void) write32(&clk_rst->rst_cpug_cmplx_clr, CRC_RST_CPUG_CLR_NONCPU); // Disable the various resets on the CPUs. write32(&clk_rst->rst_cpug_cmplx_clr, - CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG); + CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | + CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | + CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | + CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | + CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | + CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | + CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | + CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | + CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG); // Disable the reset on the non-CPU parts of the slow cluster. write32(&clk_rst->rst_cpulp_cmplx_clr, CRC_RST_CPULP_CLR_NONCPU); // Disable the various resets on the LP CPU. write32(&clk_rst->rst_cpulp_cmplx_clr, - CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG); + CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | + CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | + CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG); } void clock_halt_avp(void) { for (;;) { write32(&flow->halt_cop_events, - FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT); + FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | + FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT); } } @@ -537,11 +563,13 @@ void clock_init(void) /* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA * features section in the TRM). */ write32(&clk_rst->clk_sys_rate, - TEGRA_HCLK_RATIO << HCLK_DIVISOR_SHIFT | TEGRA_PCLK_RATIO << PCLK_DIVISOR_SHIFT); - write32(&clk_rst->pllc_out, - CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN); - write32(&clk_rst->sclk_brst_pol, - SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); /* sclk = 300 MHz */ + TEGRA_HCLK_RATIO << HCLK_DIVISOR_SHIFT | + TEGRA_PCLK_RATIO << PCLK_DIVISOR_SHIFT); + write32(&clk_rst->pllc_out, CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ) + << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN); + write32(&clk_rst->sclk_brst_pol, /* sclk = 300 MHz */ + SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | + SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); /* Change the oscillator drive strength (from U-Boot -- why?) */ clrsetbits_le32(&clk_rst->osc_ctrl, OSC_XOFS_MASK, @@ -560,9 +588,15 @@ void clock_init(void) /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ write32(&clk_rst->pllp_outa, - (CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT); + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT); write32(&clk_rst->pllp_outb, - (CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT); + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT); /* init pllx */ init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc, diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 2ed2103d15..e8cd5716f4 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -275,7 +275,7 @@ inline static uint32_t read32(const void *addr) return *(volatile uint32_t *)addr; } -inline static void write32(uint32_t val, void *addr) +inline static void write32(void *addr, uint32_t val) { *(volatile uint32_t *)addr = val; } @@ -483,7 +483,10 @@ static void clear_cpu_resets(void) // Clear software controlled reset of the fast cluster. write32(clk_rst_rst_cpug_cmplx_clr_ptr, - CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3); + CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | + CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | + CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | + CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3); } @@ -513,8 +516,7 @@ static void power_on_partition(unsigned id) uint32_t bit = 0x1 << id; if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) { // Partition is not on. Turn it on. - write32(pmc_ctlr_pwrgate_toggle_ptr, - id | PWRGATE_TOGGLE_START); + write32(pmc_ctlr_pwrgate_toggle_ptr, id | PWRGATE_TOGGLE_START); // Wait until the partition is powerd on. while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index 70fafee83e..f1c70aa43a 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -67,8 +67,8 @@ static void tegra124_uart_init(struct tegra124_uart *uart_ptr) // Hide the divisor latches. write8(&uart_ptr->lcr, line_config); // Enable FIFOs, and clear receive and transmit. - write8(&uart_ptr->fcr, - UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); + write8(&uart_ptr->fcr, UART8250_FCR_FIFO_EN | + UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); } static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr) diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c index c13a086501..1495a9a7e8 100644 --- a/src/soc/nvidia/tegra132/clock.c +++ b/src/soc/nvidia/tegra132/clock.c @@ -243,14 +243,25 @@ static void init_utmip_pll(void) clrbits_le32(CLK_RST_REG(utmip_pll_cfg2), 1 << 30); /* PHY_XTAL_CLKEN */ udelay(1); - write32(CLK_RST_REG(utmip_pll_cfg0), 80 << 16 | 1 << 8 | 0);/* 960MHz * 1 / 80 == 12 MHz */ + write32(CLK_RST_REG(utmip_pll_cfg0), /* 960MHz * 1 / 80 == 12 MHz */ + 80 << 16 | /* (rst) phy_divn */ + 1 << 8); /* (rst) phy_divm */ write32(CLK_RST_REG(utmip_pll_cfg1), - div_round_up(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | div_round_up(khz, 102) << 0 | 0); + div_round_up(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */ + 0 << 16 | /* PLLU pwrdn */ + 0 << 14 | /* pll_enable pwrdn */ + 0 << 12 | /* pll_active pwrdn */ + div_round_up(khz, 102) << 0); /* phy_stbl_cnt / 256 (2.5ms) */ /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */ write32(CLK_RST_REG(utmip_pll_cfg2), - 0 << 24 | div_round_up(khz, 3200) << 18 | div_round_up(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0); + 0 << 24 | /* SAMP_D/XDEV pwrdn */ + div_round_up(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */ + div_round_up(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */ + 0 << 4 | /* SAMP_C/USB3 pwrdn */ + 0 << 2 | /* SAMP_B/XHOST pwrdn */ + 0 << 0); /* SAMP_A/USBD pwrdn */ setbits_le32(CLK_RST_REG(utmip_pll_cfg2), 1 << 30); /* PHY_XTAL_CLKEN */ } @@ -388,7 +399,8 @@ u32 clock_configure_plld(u32 frequency) void clock_early_uart(void) { write32(CLK_RST_REG(clk_src_uarta), - CLK_SRC_DEV_ID(UARTA, CLK_M) << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900)); + CLK_SRC_DEV_ID(UARTA, CLK_M) << CLK_SOURCE_SHIFT | + CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900)); clock_enable_clear_reset_l(CLK_L_UARTA); } @@ -513,7 +525,8 @@ void clock_halt_avp(void) { for (;;) write32(&flow->halt_cop_events, - FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT); + FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | + FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT); } void clock_init(void) @@ -529,12 +542,14 @@ void clock_init(void) /* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA * features section in the TRM). */ - write32(CLK_RST_REG(clk_sys_rate), - 1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT); /* pclk = hclk = sclk/2 */ + write32(CLK_RST_REG(clk_sys_rate), /* pclk = hclk = sclk/2 */ + 1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT); write32(CLK_RST_REG(pllc_out), - CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN); - write32(CLK_RST_REG(sclk_brst_pol), - SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); /* sclk = 300 MHz */ + CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_CLKEN | PLL_OUT_RSTN); + write32(CLK_RST_REG(sclk_brst_pol), /* sclk = 300 MHz */ + SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | + SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); /* Change the oscillator drive strength (from U-Boot -- why?) */ clrsetbits_le32(CLK_RST_REG(osc_ctrl), OSC_XOFS_MASK, @@ -550,9 +565,15 @@ void clock_init(void) /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ write32(CLK_RST_REG(pllp_outa), - (CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT); + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT); write32(CLK_RST_REG(pllp_outb), - (CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT); + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT); /* init pllu */ init_pll(CLK_RST_REG(pllu_base), CLK_RST_REG(pllu_misc), diff --git a/src/soc/nvidia/tegra132/include/soc/tegra_dsi.h b/src/soc/nvidia/tegra132/include/soc/tegra_dsi.h index 830257d7cc..4e03d93cb4 100644 --- a/src/soc/nvidia/tegra132/include/soc/tegra_dsi.h +++ b/src/soc/nvidia/tegra132/include/soc/tegra_dsi.h @@ -207,13 +207,13 @@ struct tegra_dsi { static inline unsigned long tegra_dsi_readl(struct tegra_dsi *dsi, unsigned long reg) { - return readl(dsi->regs + (reg << 2)); + return read32(dsi->regs + (reg << 2)); } static inline void tegra_dsi_writel(struct tegra_dsi *dsi, unsigned long value, unsigned long reg) { - writel(value, dsi->regs + (reg << 2)); + write32(dsi->regs + (reg << 2), value); } #endif /* __TEGRA_DSI_H__ */ diff --git a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c index 8392a58228..621c4b72e3 100644 --- a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c @@ -254,7 +254,7 @@ inline static uint32_t read32(const void *addr) return *(volatile uint32_t *)addr; } -inline static void write32(uint32_t val, void *addr) +inline static void write32(void *addr, uint32_t val) { *(volatile uint32_t *)addr = val; } @@ -542,8 +542,7 @@ static void power_on_partition(unsigned id) uint32_t bit = 0x1 << id; if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) { // Partition is not on. Turn it on. - write32(pmc_ctlr_pwrgate_toggle_ptr, - id | PWRGATE_TOGGLE_START); + write32(pmc_ctlr_pwrgate_toggle_ptr, id | PWRGATE_TOGGLE_START); // Wait until the partition is powerd on. while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) diff --git a/src/soc/nvidia/tegra132/spi.c b/src/soc/nvidia/tegra132/spi.c index 33620fb202..6fd1933b92 100644 --- a/src/soc/nvidia/tegra132/spi.c +++ b/src/soc/nvidia/tegra132/spi.c @@ -494,7 +494,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, dcache_clean_by_mva(spi->out_buf, bytes); write32(&spi->dma_out->regs->apb_ptr, - (uintptr_t) & spi->regs->tx_fifo); + (uintptr_t)&spi->regs->tx_fifo); write32(&spi->dma_out->regs->ahb_ptr, (uintptr_t)spi->out_buf); setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_out); diff --git a/src/soc/nvidia/tegra132/uart.c b/src/soc/nvidia/tegra132/uart.c index e7b7ca9f69..386eaf9005 100644 --- a/src/soc/nvidia/tegra132/uart.c +++ b/src/soc/nvidia/tegra132/uart.c @@ -74,8 +74,8 @@ static void tegra132_uart_init(struct tegra132_uart *uart_ptr) // Hide the divisor latches. write8(&uart_ptr->lcr, line_config); // Enable FIFOs, and clear receive and transmit. - write8(&uart_ptr->fcr, - UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); + write8(&uart_ptr->fcr, UART8250_FCR_FIFO_EN | + UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); } static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr) diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c index 0ffd83f032..d30771fb2e 100644 --- a/src/soc/qualcomm/ipq806x/clock.c +++ b/src/soc/qualcomm/ipq806x/clock.c @@ -136,7 +136,12 @@ void usb_clock_config(void) write32(USB30_1_MOC_UTMI_CLK_CTL, 0x10); write32(USB30_RESET, - 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0 | 0); + 1 << 5 | /* assert port2 HS PHY async reset */ + 1 << 4 | /* assert master async reset */ + 1 << 3 | /* assert sleep async reset */ + 1 << 2 | /* assert MOC UTMI async reset */ + 1 << 1 | /* assert power-on async reset */ + 1 << 0); /* assert PHY async reset */ udelay(5); write32(USB30_RESET, 0); /* deassert all USB resets again */ } diff --git a/src/soc/qualcomm/ipq806x/include/soc/iomap.h b/src/soc/qualcomm/ipq806x/include/soc/iomap.h index f2500f1cbf..4a3aa49140 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/soc/iomap.h @@ -44,8 +44,8 @@ macros for read/write. Hence, special macros for readl_i and writel_i are included to do this in one place for all occurrences in vendor code */ -#define readl_i(a) readl((const void *)(a)) -#define writel_i(v,a) writel(v,(void *)a) +#define readl_i(a) read32((const void *)(a)) +#define writel_i(v,a) write32((void *)a, v) #define clrsetbits_le32_i(addr, clear, set) \ clrsetbits_le32(((void *)(addr)), (clear), (set)) diff --git a/src/soc/qualcomm/ipq806x/qup.c b/src/soc/qualcomm/ipq806x/qup.c index bc78e7c67a..a497514baf 100644 --- a/src/soc/qualcomm/ipq806x/qup.c +++ b/src/soc/qualcomm/ipq806x/qup.c @@ -167,10 +167,10 @@ static qup_return_t qup_i2c_write_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj, while (data_len) { if (data_len == 1 && stop_seq) { write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO), - (QUP_I2C_STOP_SEQ | QUP_I2C_DATA(data_ptr[idx]))); + QUP_I2C_STOP_SEQ | QUP_I2C_DATA(data_ptr[idx])); } else { write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO), - (QUP_I2C_DATA_SEQ | QUP_I2C_DATA(data_ptr[idx]))); + QUP_I2C_DATA_SEQ | QUP_I2C_DATA(data_ptr[idx])); } data_len--; idx++; @@ -235,10 +235,10 @@ static qup_return_t qup_i2c_read_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj) qup_set_state(gsbi_id, QUP_STATE_RUN); write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO), - (QUP_I2C_START_SEQ | (QUP_I2C_ADDR(addr) | QUP_I2C_SLAVE_READ))); + QUP_I2C_START_SEQ | (QUP_I2C_ADDR(addr) | QUP_I2C_SLAVE_READ)); write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO), - (QUP_I2C_RECV_SEQ | data_len)); + QUP_I2C_RECV_SEQ | data_len); ret = qup_fifo_wait_while(gsbi_id, OUTPUT_FIFO_NOT_EMPTY); if (ret) diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c index d7dac7243c..72ec19ecdf 100644 --- a/src/soc/qualcomm/ipq806x/usb.c +++ b/src/soc/qualcomm/ipq806x/usb.c @@ -102,15 +102,32 @@ static struct usb_dwc3 * const usb_host2_dwc3 = (void *)USB_HOST2_DWC3_BASE; static void setup_dwc3(struct usb_dwc3 *dwc3) { write32(&dwc3->usb3pipectl, - 0x1 << 31 | 0x1 << 25 | 0x1 << 24 | 0x1 << 19 | 0x1 << 18 | 0x1 << 1 | 0x1 << 0 | 0); + 0x1 << 31 | /* assert PHY soft reset */ + 0x1 << 25 | /* (default) U1/U2 exit fail -> recovery? */ + 0x1 << 24 | /* (default) activate PHY low power states */ + 0x1 << 19 | /* (default) PHY low power delay value */ + 0x1 << 18 | /* (default) activate PHY low power delay */ + 0x1 << 1 | /* (default) Tx deemphasis value */ + 0x1 << 0); /* (default) elastic buffer mode */ write32(&dwc3->usb2phycfg, - 0x1 << 31 | 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0); + 0x1 << 31 | /* assert PHY soft reset */ + 0x9 << 10 | /* (default) PHY clock turnaround 8-bit UTMI+ */ + 0x1 << 8 | /* (default) enable PHY sleep in L1 */ + 0x1 << 6); /* (default) enable PHY suspend */ write32(&dwc3->ctl, - 0x2 << 19 | 0x1 << 16 | 0x1 << 12 | 0x1 << 11 | 0x1 << 10 | 0x1 << 2 | 0); + 0x2 << 19 | /* (default) suspend clock scaling */ + 0x1 << 16 | /* retry SS three times before HS downgrade */ + 0x1 << 12 | /* port capability HOST */ + 0x1 << 11 | /* assert core soft reset */ + 0x1 << 10 | /* (default) sync ITP to refclk */ + 0x1 << 2); /* U2 exit after 8us LFPS (instead of 248ns) */ - write32(&dwc3->uctl, 0x32 << 22 | 0x1 << 15 | 0x10 << 0 | 0); + write32(&dwc3->uctl, + 0x32 << 22 | /* (default) reference clock period in ns */ + 0x1 << 15 | /* (default) XHCI compliant device addressing */ + 0x10 << 0); /* (default) devices time out after 32us */ udelay(5); @@ -122,13 +139,31 @@ static void setup_dwc3(struct usb_dwc3 *dwc3) static void setup_phy(struct usb_qc_phy *phy) { write32(&phy->ss_phy_ctrl, - 0x1 << 24 | 0x1 << 8 | 0x1 << 7 | 0x19 << 0 | 0); + 0x1 << 24 | /* Indicate VBUS power present */ + 0x1 << 8 | /* Enable USB3 ref clock to prescaler */ + 0x1 << 7 | /* assert SS PHY reset */ + 0x19 << 0); /* (default) reference clock multiplier */ write32(&phy->hs_phy_ctrl, - 0x1 << 26 | 0x1 << 25 | 0x1 << 24 | 0x1 << 21 | 0x1 << 20 | 0x1 << 18 | 0x1 << 17 | 0x1 << 11 | 0x1 << 9 | 0x1 << 8 | 0x1 << 7 | 0x7 << 4 | 0x1 << 1 | 0); + 0x1 << 26 | /* (default) unclamp DPSE/DMSE VLS */ + 0x1 << 25 | /* (default) select freeclk for utmi_clk */ + 0x1 << 24 | /* (default) unclamp DMSE VLS */ + 0x1 << 21 | /* (default) enable UTMI clock */ + 0x1 << 20 | /* set OTG VBUS as valid */ + 0x1 << 18 | /* use ref clock from core */ + 0x1 << 17 | /* (default) unclamp DPSE VLS */ + 0x1 << 11 | /* force xo/bias/pll to stay on in suspend */ + 0x1 << 9 | /* (default) unclamp IDHV */ + 0x1 << 8 | /* (default) unclamp VLS (again???) */ + 0x1 << 7 | /* (default) unclamp HV VLS */ + 0x7 << 4 | /* select frequency (no idea which one) */ + 0x1 << 1); /* (default) "retention enable" */ write32(&phy->ss_phy_param1, - 0x6e << 20 | 0x20 << 14 | 0x17 << 8 | 0x9 << 3 | 0); + 0x6e << 20 | /* full TX swing amplitude */ + 0x20 << 14 | /* (default) 6dB TX deemphasis */ + 0x17 << 8 | /* 3.5dB TX deemphasis */ + 0x9 << 3); /* (default) LoS detector level */ write32(&phy->general_cfg, 0x1 << 2); /* set XHCI 1.00 compliance */ diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index a9c888d631..89503e51db 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -220,7 +220,8 @@ static int rkclk_set_pll(u32 *pll_con, const struct pll_div *div) write32(&pll_con[3], RK_SETBITS(PLL_RESET_MSK)); write32(&pll_con[0], - RK_CLRSETBITS(PLL_NR_MSK, (div->nr - 1) << PLL_NR_SHIFT) | RK_CLRSETBITS(PLL_OD_MSK, (div->no - 1))); + RK_CLRSETBITS(PLL_NR_MSK, (div->nr - 1) << PLL_NR_SHIFT) | + RK_CLRSETBITS(PLL_OD_MSK, (div->no - 1))); write32(&pll_con[1], RK_CLRSETBITS(PLL_NF_MSK, (div->nf - 1))); @@ -259,7 +260,8 @@ void rkclk_init(void) /* pll enter slow-mode */ write32(&cru_ptr->cru_mode_con, - RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_SLOW) | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_SLOW)); + RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_SLOW) | + RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_SLOW)); /* init pll */ rkclk_set_pll(&cru_ptr->cru_gpll_con[0], &gpll_init_cfg); @@ -288,8 +290,14 @@ void rkclk_init(void) assert((pclk_div + 1) * PD_BUS_PCLK_HZ == PD_BUS_ACLK_HZ && pclk_div < 0x7); - write32(&cru_ptr->cru_clksel_con[1], - RK_SETBITS(PD_BUS_SEL_GPLL) | RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK, pclk_div << PD_BUS_PCLK_DIV_SHIFT) | RK_CLRSETBITS(PD_BUS_HCLK_DIV_MSK, hclk_div << PD_BUS_HCLK_DIV_SHIFT) | RK_CLRSETBITS(PD_BUS_ACLK_DIV0_MASK, aclk_div << PD_BUS_ACLK_DIV0_SHIFT) | RK_CLRSETBITS(PD_BUS_ACLK_DIV1_MASK, 0 << 0)); + write32(&cru_ptr->cru_clksel_con[1], RK_SETBITS(PD_BUS_SEL_GPLL) | + RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK, + pclk_div << PD_BUS_PCLK_DIV_SHIFT) | + RK_CLRSETBITS(PD_BUS_HCLK_DIV_MSK, + hclk_div << PD_BUS_HCLK_DIV_SHIFT) | + RK_CLRSETBITS(PD_BUS_ACLK_DIV0_MASK, + aclk_div << PD_BUS_ACLK_DIV0_SHIFT) | + RK_CLRSETBITS(PD_BUS_ACLK_DIV1_MASK, 0 << 0)); /* * peri clock pll source selection and @@ -306,12 +314,18 @@ void rkclk_init(void) assert((1 << pclk_div) * PERI_PCLK_HZ == PERI_ACLK_HZ && (pclk_div < 0x4)); - write32(&cru_ptr->cru_clksel_con[10], - RK_SETBITS(PERI_SEL_GPLL) | RK_CLRSETBITS(PERI_PCLK_DIV_MSK, pclk_div << PERI_PCLK_DIV_SHIFT) | RK_CLRSETBITS(PERI_HCLK_DIV_MSK, hclk_div << PERI_HCLK_DIV_SHIFT) | RK_CLRSETBITS(PERI_ACLK_DIV_MSK, aclk_div << PERI_ACLK_DIV_SHIFT)); + write32(&cru_ptr->cru_clksel_con[10], RK_SETBITS(PERI_SEL_GPLL) | + RK_CLRSETBITS(PERI_PCLK_DIV_MSK, + pclk_div << PERI_PCLK_DIV_SHIFT) | + RK_CLRSETBITS(PERI_HCLK_DIV_MSK, + hclk_div << PERI_HCLK_DIV_SHIFT) | + RK_CLRSETBITS(PERI_ACLK_DIV_MSK, + aclk_div << PERI_ACLK_DIV_SHIFT)); /* PLL enter normal-mode */ write32(&cru_ptr->cru_mode_con, - RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM) | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM)); + RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM) | + RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM)); } @@ -336,15 +350,19 @@ void rkclk_configure_cpu(void) * core clock select apll, apll clk = 1800MHz * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz */ - write32(&cru_ptr->cru_clksel_con[0], - RK_CLRBITS(CORE_SEL_PLL_MSK) | RK_CLRSETBITS(A12_DIV_MSK, 0 << A12_DIV_SHIFT) | RK_CLRSETBITS(MP_DIV_MSK, 3 << MP_DIV_SHIFT) | RK_CLRSETBITS(M0_DIV_MSK, 1 << 0)); + write32(&cru_ptr->cru_clksel_con[0], RK_CLRBITS(CORE_SEL_PLL_MSK) | + RK_CLRSETBITS(A12_DIV_MSK, 0 << A12_DIV_SHIFT) | + RK_CLRSETBITS(MP_DIV_MSK, 3 << MP_DIV_SHIFT) | + RK_CLRSETBITS(M0_DIV_MSK, 1 << 0)); /* * set up dependent divisors for L2RAM/ATCLK and PCLK clocks. * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz */ write32(&cru_ptr->cru_clksel_con[37], - RK_CLRSETBITS(L2_DIV_MSK, 1 << 0) | RK_CLRSETBITS(ATCLK_DIV_MSK, (3 << ATCLK_DIV_SHIFT)) | RK_CLRSETBITS(PCLK_DBG_DIV_MSK, (3 << PCLK_DBG_DIV_SHIFT))); + RK_CLRSETBITS(L2_DIV_MSK, 1 << 0) | + RK_CLRSETBITS(ATCLK_DIV_MSK, (3 << ATCLK_DIV_SHIFT)) | + RK_CLRSETBITS(PCLK_DBG_DIV_MSK, (3 << PCLK_DBG_DIV_SHIFT))); /* PLL enter normal-mode */ write32(&cru_ptr->cru_mode_con, @@ -399,7 +417,12 @@ void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy) u32 phy_srstn_shift = 5 * ch; write32(&cru_ptr->cru_softrst_con[10], - RK_CLRSETBITS(1 << phy_ctl_srstn_shift, phy << phy_ctl_srstn_shift) | RK_CLRSETBITS(1 << ctl_psrstn_shift, ctl << ctl_psrstn_shift) | RK_CLRSETBITS(1 << ctl_srstn_shift, ctl << ctl_srstn_shift) | RK_CLRSETBITS(1 << phy_psrstn_shift, phy << phy_psrstn_shift) | RK_CLRSETBITS(1 << phy_srstn_shift, phy << phy_srstn_shift)); + RK_CLRSETBITS(1 << phy_ctl_srstn_shift, + phy << phy_ctl_srstn_shift) | + RK_CLRSETBITS(1 << ctl_psrstn_shift, ctl << ctl_psrstn_shift) | + RK_CLRSETBITS(1 << ctl_srstn_shift, ctl << ctl_srstn_shift) | + RK_CLRSETBITS(1 << phy_psrstn_shift, phy << phy_psrstn_shift) | + RK_CLRSETBITS(1 << phy_srstn_shift, phy << phy_srstn_shift)); } void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n) @@ -407,7 +430,8 @@ void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n) u32 phy_ctl_srstn_shift = 4 + 5 * ch; write32(&cru_ptr->cru_softrst_con[10], - RK_CLRSETBITS(1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift)); + RK_CLRSETBITS(1 << phy_ctl_srstn_shift, + n << phy_ctl_srstn_shift)); } void rkclk_configure_spi(unsigned int bus, unsigned int hz) @@ -419,15 +443,18 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz) switch (bus) { /*select gpll as spi src clk, and set div*/ case 0: write32(&cru_ptr->cru_clksel_con[25], - RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7 | (src_clk_div - 1) << 0)); + RK_CLRSETBITS(1 << 7 | 0x1f << 0, + 1 << 7 | (src_clk_div - 1) << 0)); break; case 1: write32(&cru_ptr->cru_clksel_con[25], - RK_CLRSETBITS(1 << 15 | 0x1f << 8, 1 << 15 | (src_clk_div - 1) << 8)); + RK_CLRSETBITS(1 << 15 | 0x1f << 8, + 1 << 15 | (src_clk_div - 1) << 8)); break; case 2: write32(&cru_ptr->cru_clksel_con[39], - RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7 | (src_clk_div - 1) << 0)); + RK_CLRSETBITS(1 << 7 | 0x1f << 0, + 1 << 7 | (src_clk_div - 1) << 0)); break; default: printk(BIOS_ERR, "do not support this spi bus\n"); @@ -454,7 +481,8 @@ void rkclk_configure_i2s(unsigned int hz) i2s0_clk_sel: divider ouput from fraction i2s0_pll_div_con: 0*/ write32(&cru_ptr->cru_clksel_con[4], - RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0, 1 << 15 | 0 << 12 | 1 << 8 | 0 << 0)); + RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0, + 1 << 15 | 0 << 12 | 1 << 8 | 0 << 0)); /* set frac divider */ v = clk_gcd(GPLL_HZ, hz); @@ -569,12 +597,14 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) switch (vop_id) { case 0: write32(&cru_ptr->cru_clksel_con[31], - RK_CLRSETBITS(3 << 6 | 0x1f << 0, 0 << 6 | (div - 1) << 0)); + RK_CLRSETBITS(3 << 6 | 0x1f << 0, + 0 << 6 | (div - 1) << 0)); break; case 1: write32(&cru_ptr->cru_clksel_con[31], - RK_CLRSETBITS(3 << 14 | 0x1f << 8, 0 << 14 | (div - 1) << 8)); + RK_CLRSETBITS(3 << 14 | 0x1f << 8, + 0 << 14 | (div - 1) << 8)); break; } } diff --git a/src/soc/rockchip/rk3288/edp.c b/src/soc/rockchip/rk3288/edp.c index 38e972d7cd..e0590ab97f 100644 --- a/src/soc/rockchip/rk3288/edp.c +++ b/src/soc/rockchip/rk3288/edp.c @@ -57,25 +57,27 @@ static void rk_edp_init_refclk(struct rk_edp *edp) write32(&edp->regs->pll_reg_1, REF_CLK_24M); /*initial value*/ - write32(&edp->regs->pll_reg_2, - LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US | V2L_CUR_SEL_1MA); + write32(&edp->regs->pll_reg_2, LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | + CHG_PUMP_CUR_SEL_5US | V2L_CUR_SEL_1MA); - write32(&edp->regs->pll_reg_3, - LOCK_DET_CNT_SEL_256 | LOOP_FILTER_RESET | PALL_SSC_RESET | LOCK_DET_BYPASS | PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE); + write32(&edp->regs->pll_reg_3, LOCK_DET_CNT_SEL_256 | + LOOP_FILTER_RESET | PALL_SSC_RESET | LOCK_DET_BYPASS | + PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE); - write32(&edp->regs->pll_reg_5, - REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL | CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP); + write32(&edp->regs->pll_reg_5, REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL | + CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP); write32(&edp->regs->ssc_reg, SSC_OFFSET | SSC_MODE | SSC_DEPTH); - write32(&edp->regs->tx_common, - TX_SWING_PRE_EMP_MODE | PRE_DRIVER_PW_CTRL1 | LP_MODE_CLK_REGULATOR | RESISTOR_MSB_CTRL | RESISTOR_CTRL); + write32(&edp->regs->tx_common, TX_SWING_PRE_EMP_MODE | + PRE_DRIVER_PW_CTRL1 | LP_MODE_CLK_REGULATOR | + RESISTOR_MSB_CTRL | RESISTOR_CTRL); - write32(&edp->regs->dp_aux, - DP_AUX_COMMON_MODE | DP_AUX_EN | AUX_TERM_50OHM); + write32(&edp->regs->dp_aux, DP_AUX_COMMON_MODE | + DP_AUX_EN | AUX_TERM_50OHM); - write32(&edp->regs->dp_bias, - DP_BG_OUT_SEL | DP_DB_CUR_CTRL | DP_BG_SEL | DP_RESISTOR_TUNE_BG); + write32(&edp->regs->dp_bias, DP_BG_OUT_SEL | DP_DB_CUR_CTRL | + DP_BG_SEL | DP_RESISTOR_TUNE_BG); write32(&edp->regs->dp_reserv2, CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL); diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index 5fc9c7b185..96b8354087 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -53,7 +53,8 @@ static void __gpio_input(gpio_t gpio, u32 pull) 3 << (gpio.idx * 2), pull << (gpio.idx * 2)); else write32(&rk3288_grf->gpio1_p[(gpio.port - 1)][gpio.bank], - RK_CLRSETBITS(3 << (gpio.idx * 2), pull << (gpio.idx * 2))); + RK_CLRSETBITS(3 << (gpio.idx * 2), + pull << (gpio.idx * 2))); } void gpio_input(gpio_t gpio) diff --git a/src/soc/rockchip/rk3288/pwm.c b/src/soc/rockchip/rk3288/pwm.c index fb47dc8312..9f993f707f 100644 --- a/src/soc/rockchip/rk3288/pwm.c +++ b/src/soc/rockchip/rk3288/pwm.c @@ -75,8 +75,9 @@ void pwm_init(u32 id, u32 period_ns, u32 duty_ns) /*use rk pwm*/ write32(&rk3288_grf->soc_con2, RK_SETBITS(1 << 0)); - write32(&rk3288_pwm->pwm[id].pwm_ctrl, - PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE | RK_PWM_DISABLE); + write32(&rk3288_pwm->pwm[id].pwm_ctrl, PWM_SEL_SRC_CLK | + PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_CONTINUOUS | + PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE | RK_PWM_DISABLE); period = (PD_BUS_PCLK_HZ / 1000) * period_ns / USECS_PER_SEC; duty = (PD_BUS_PCLK_HZ / 1000) * duty_ns / USECS_PER_SEC; diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 86acf6dc3f..e7d33ea3a6 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -609,12 +609,15 @@ static void pctl_cfg(u32 channel, sdram_params->pctl_timing.tcl - 1); write32(&ddr_pctl_regs->dfitphywrlat, sdram_params->pctl_timing.tcwl); - write32(&ddr_pctl_regs->mcfg, - LPDDR2_S4 | MDDR_LPDDR2_CLK_STOP_IDLE(0) | LPDDR2_EN | BURSTLENGTH_CFG(burstlen) | TFAW_CFG(6) | PD_EXIT_FAST | PD_TYPE(1) | PD_IDLE(0)); + write32(&ddr_pctl_regs->mcfg, LPDDR2_S4 | + MDDR_LPDDR2_CLK_STOP_IDLE(0) | LPDDR2_EN | + BURSTLENGTH_CFG(burstlen) | TFAW_CFG(6) | + PD_EXIT_FAST | PD_TYPE(1) | PD_IDLE(0)); write32(&rk3288_grf->soc_con0, MSCH_MAINDDR3(channel, 0)); - write32(&rk3288_grf->soc_con2, - PUBL_LPDDR3_EN(channel, 1) | PCTL_BST_DISABLE(channel, 1) | PCTL_LPDDR3_ODT_EN(channel, sdram_params->odt)); + write32(&rk3288_grf->soc_con2, PUBL_LPDDR3_EN(channel, 1) | + PCTL_BST_DISABLE(channel, 1) | + PCTL_LPDDR3_ODT_EN(channel, sdram_params->odt)); break; case DDR3: @@ -627,11 +630,14 @@ static void pctl_cfg(u32 channel, write32(&ddr_pctl_regs->dfitphywrlat, sdram_params->pctl_timing.tcwl - 1); write32(&ddr_pctl_regs->mcfg, - MDDR_LPDDR2_CLK_STOP_IDLE(0) | DDR3_EN | DDR2_DDR3_BL_8 | TFAW_CFG(6) | PD_EXIT_SLOW | PD_TYPE(1) | PD_IDLE(0)); + MDDR_LPDDR2_CLK_STOP_IDLE(0) | DDR3_EN | + DDR2_DDR3_BL_8 | TFAW_CFG(6) | + PD_EXIT_SLOW | PD_TYPE(1) | PD_IDLE(0)); write32(&rk3288_grf->soc_con0, MSCH_MAINDDR3(channel, 1)); - write32(&rk3288_grf->soc_con2, - PUBL_LPDDR3_EN(channel, 0) | PCTL_BST_DISABLE(channel, 0) | PCTL_LPDDR3_ODT_EN(channel, 0)); + write32(&rk3288_grf->soc_con2, PUBL_LPDDR3_EN(channel, 0) | + PCTL_BST_DISABLE(channel, 0) | + PCTL_LPDDR3_ODT_EN(channel, 0)); break; } @@ -656,11 +662,14 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) write32(&msch_regs->devtodev, BUSWRTORD(2) | BUSRDTOWR(2) | BUSRDTORD(1)); write32(&ddr_publ_regs->ptr[0], - PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq / MHz * 5120, 1000)) | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq / MHz * 50, 1000)) | PRT_ITMSRST(8)); + PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq / MHz * 5120, 1000)) + | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq / MHz * 50, 1000)) + | PRT_ITMSRST(8)); write32(&ddr_publ_regs->ptr[1], - PRT_DINIT0(div_round_up(sdram_params->ddr_freq / MHz * 500000, 1000)) | PRT_DINIT1(div_round_up(sdram_params->ddr_freq / MHz * 400, 1000))); - write32(&ddr_publ_regs->ptr[2], - PRT_DINIT2(MIN(dinit2, 0x1ffff)) | PRT_DINIT3(div_round_up(sdram_params->ddr_freq / MHz * 1000, 1000))); + PRT_DINIT0(div_round_up(sdram_params->ddr_freq / MHz * 500000, 1000)) + | PRT_DINIT1(div_round_up(sdram_params->ddr_freq / MHz * 400, 1000))); + write32(&ddr_publ_regs->ptr[2], PRT_DINIT2(MIN(dinit2, 0x1ffff)) + | PRT_DINIT3(div_round_up(sdram_params->ddr_freq / MHz * 1000, 1000))); switch (sdram_params->dramtype) { case LPDDR3: diff --git a/src/soc/rockchip/rk3288/uart.c b/src/soc/rockchip/rk3288/uart.c index 8ba1fdee73..7710c99760 100644 --- a/src/soc/rockchip/rk3288/uart.c +++ b/src/soc/rockchip/rk3288/uart.c @@ -103,8 +103,8 @@ static void rk3288_uart_init(void) // Hide the divisor latches. write32(&uart_ptr->lcr, line_config); // Enable FIFOs, and clear receive and transmit. - write32(&uart_ptr->fcr, - UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); + write32(&uart_ptr->fcr, UART8250_FCR_FIFO_EN | + UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); } static void rk3288_uart_tx_byte(unsigned char data) diff --git a/src/soc/rockchip/rk3288/vop.c b/src/soc/rockchip/rk3288/vop.c index 915d452d4b..81fc41e991 100644 --- a/src/soc/rockchip/rk3288/vop.c +++ b/src/soc/rockchip/rk3288/vop.c @@ -51,11 +51,11 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid) write32(&preg->win0_act_info, V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1)); - write32(&preg->win0_dsp_st, - V_DSP_XST(xpos + hsync_len + hback_porch) | V_DSP_YST(ypos + vsync_len + vback_porch)); + write32(&preg->win0_dsp_st, V_DSP_XST(xpos + hsync_len + hback_porch) | + V_DSP_YST(ypos + vsync_len + vback_porch)); - write32(&preg->win0_dsp_info, - V_DSP_WIDTH(hactive - 1) | V_DSP_HEIGHT(vactive - 1)); + write32(&preg->win0_dsp_info, V_DSP_WIDTH(hactive - 1) | + V_DSP_HEIGHT(vactive - 1)); clrsetbits_le32(&preg->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, V_WIN0_KEY_EN(0) | @@ -111,23 +111,27 @@ void rkvop_mode_set(u32 vop_id, const struct edid *edid) clrsetbits_le32(&preg->sys_ctrl, M_ALL_OUT_EN, V_EDP_OUT_EN(1)); clrsetbits_le32(&preg->dsp_ctrl0, M_DSP_OUT_MODE, V_DSP_OUT_MODE(15)); - write32(&preg->dsp_htotal_hs_end, - V_HSYNC(hsync_len) | V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch)); + write32(&preg->dsp_htotal_hs_end, V_HSYNC(hsync_len) | + V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch)); write32(&preg->dsp_hact_st_end, - V_HEAP(hsync_len + hback_porch + hactive) | V_HASP(hsync_len + hback_porch)); + V_HEAP(hsync_len + hback_porch + hactive) | + V_HASP(hsync_len + hback_porch)); - write32(&preg->dsp_vtotal_vs_end, - V_VSYNC(vsync_len) | V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch)); + write32(&preg->dsp_vtotal_vs_end, V_VSYNC(vsync_len) | + V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch)); write32(&preg->dsp_vact_st_end, - V_VAEP(vsync_len + vback_porch + vactive) | V_VASP(vsync_len + vback_porch)); + V_VAEP(vsync_len + vback_porch + vactive) | + V_VASP(vsync_len + vback_porch)); write32(&preg->post_dsp_hact_info, - V_HEAP(hsync_len + hback_porch + hactive) | V_HASP(hsync_len + hback_porch)); + V_HEAP(hsync_len + hback_porch + hactive) | + V_HASP(hsync_len + hback_porch)); write32(&preg->post_dsp_vact_info, - V_VAEP(vsync_len + vback_porch + vactive) | V_VASP(vsync_len + vback_porch)); + V_VAEP(vsync_len + vback_porch + vactive) | + V_VASP(vsync_len + vback_porch)); write32(&preg->reg_cfg_done, 0x01); /* enable reg config */ } diff --git a/src/soc/samsung/exynos5250/clock_init.c b/src/soc/samsung/exynos5250/clock_init.c index 9cdd729f57..6f9614a0e6 100644 --- a/src/soc/samsung/exynos5250/clock_init.c +++ b/src/soc/samsung/exynos5250/clock_init.c @@ -224,8 +224,8 @@ void system_clock_init(struct mem_timings *mem, ; if (mem->use_bpll) { - write32(&exynos_clock->src_cdrex, - MUX_BPLL_SEL_MASK | MUX_MCLK_CDREX_SEL | MUX_MCLK_DPHY_SEL); + write32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK | + MUX_MCLK_CDREX_SEL | MUX_MCLK_DPHY_SEL); } else { write32(&exynos_clock->src_cdrex, CLK_REG_DISABLE); } diff --git a/src/soc/samsung/exynos5250/dmc_init_ddr3.c b/src/soc/samsung/exynos5250/dmc_init_ddr3.c index 5a3cf3ef06..7bdbd6da14 100644 --- a/src/soc/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5250/dmc_init_ddr3.c @@ -86,8 +86,9 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, write32(&exynos_phy0_control->phy_con14, mem->phy0_pulld_dqs); write32(&exynos_phy1_control->phy_con14, mem->phy1_pulld_dqs); - write32(&exynos_dmc->concontrol, - mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT)); + write32(&exynos_dmc->concontrol, mem->concontrol | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | + (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT)); update_reset_dll(exynos_dmc, DDR_MODE_DDR3); @@ -137,7 +138,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, /* Power Down mode Configuration */ write32(&exynos_dmc->pwrdnconfig, - mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT); + mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | + mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT); /* TimingRow, TimingData, TimingPower and Timingaref * values as per Memory AC parameters @@ -243,7 +245,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, write32(&exynos_dmc->memcontrol, mem->memcontrol); /* Set DMC Concontrol and enable auto-refresh counter */ - write32(&exynos_dmc->concontrol, - mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT)); + write32(&exynos_dmc->concontrol, mem->concontrol | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | + (mem->aref_en << CONCONTROL_AREF_EN_SHIFT)); return 0; } diff --git a/src/soc/samsung/exynos5250/usb.c b/src/soc/samsung/exynos5250/usb.c index 3f6833657b..2dca58e553 100644 --- a/src/soc/samsung/exynos5250/usb.c +++ b/src/soc/samsung/exynos5250/usb.c @@ -52,12 +52,22 @@ static void setup_dwc3(struct exynos5_usb_drd_dwc3 *dwc3) /* Set relevant registers to default values (clearing all reset bits) */ write32(&dwc3->usb3pipectl, - 0x1 << 24 | 0x4 << 19 | 0x1 << 18 | 0x1 << 17 | 0x1 << 1 | 0); + 0x1 << 24 | /* activate PHY low power states */ + 0x4 << 19 | /* low power delay value */ + 0x1 << 18 | /* activate PHY low power delay */ + 0x1 << 17 | /* enable SuperSpeed PHY suspend */ + 0x1 << 1); /* default Tx deemphasis value */ /* Configure PHY clock turnaround for 8-bit UTMI+, disable suspend */ - write32(&dwc3->usb2phycfg, 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0); + write32(&dwc3->usb2phycfg, + 0x9 << 10 | /* PHY clock turnaround for 8-bit UTMI+ */ + 0x1 << 8 | /* enable PHY sleep in L1 */ + 0x1 << 6); /* enable PHY suspend */ - write32(&dwc3->ctl, 0x5dc << 19 | 0x1 << 16 | 0x1 << 12 | 0); + write32(&dwc3->ctl, + 0x5dc << 19 | /* suspend clock scale for 24MHz */ + 0x1 << 16 | /* retry SS three times (bugfix from U-Boot) */ + 0x1 << 12); /* port capability HOST */ } void setup_usb_drd_dwc3() @@ -77,13 +87,32 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) write32(&phy->utmi, 1 << 6); write32(&phy->clkrst, - 0x88 << 23 | 0x1 << 20 | 0x1 << 19 | 0x68 << 11 | 0x5 << 5 | 0x1 << 4 | 0x3 << 2 | 0x1 << 1 | 0x1 << 0 | 0); + 0x88 << 23 | /* spread spectrum refclk selector */ + 0x1 << 20 | /* enable spread spectrum */ + 0x1 << 19 | /* enable prescaler refclk */ + 0x68 << 11 | /* multiplier for 24MHz refclk */ + 0x5 << 5 | /* select 24MHz refclk (weird, from U-Boot) */ + 0x1 << 4 | /* power supply in normal operating mode */ + 0x3 << 2 | /* use external refclk (undocumented on 5420?)*/ + 0x1 << 1 | /* force port reset */ + 0x1 << 0); /* normal operating mode */ write32(&phy->param0, - 0x9 << 26 | 0x3 << 22 | 0x1 << 20 | 0x1 << 18 | 0x3 << 13 | 0x3 << 9 | 0x3 << 6 | 0x4 << 3 | 0x4 << 0 | 0); + 0x9 << 26 | /* LOS level */ + 0x3 << 22 | /* TX VREF tune */ + 0x1 << 20 | /* TX rise tune */ + 0x1 << 18 | /* TX res tune */ + 0x3 << 13 | /* TX HS X Vtune */ + 0x3 << 9 | /* TX FS/LS tune */ + 0x3 << 6 | /* SQRX tune */ + 0x4 << 3 | /* OTG tune */ + 0x4 << 0); /* comp disc tune */ write32(&phy->param1, - 0x7f << 19 | 0x7f << 12 | 0x20 << 6 | 0x1c << 0 | 0); + 0x7f << 19 | /* reserved */ + 0x7f << 12 | /* Tx launch amplitude */ + 0x20 << 6 | /* Tx deemphasis 6dB */ + 0x1c << 0); /* Tx deemphasis 3.5dB (value from U-Boot) */ /* disable all test features */ write32(&phy->test, 0); diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index 6972618ac3..5eeb07b016 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -111,10 +111,12 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) write32(&exynos_drex0->phycontrol0, val); write32(&exynos_drex1->phycontrol0, val); - write32(&exynos_drex0->concontrol, - mem->concontrol | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); - write32(&exynos_drex1->concontrol, - mem->concontrol | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); + write32(&exynos_drex0->concontrol, mem->concontrol | + (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); + write32(&exynos_drex1->concontrol, mem->concontrol | + (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); do { val = read32(&exynos_drex0->phystatus); @@ -198,9 +200,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) for (i = 0; i < 128; i++) { for (chip = 0; chip < mem->chips_to_configure; chip++) { write32(&exynos_drex0->directcmd, - DIRECT_CMD_REFA | (chip << DIRECT_CMD_CHIP_SHIFT)); + DIRECT_CMD_REFA | + (chip << DIRECT_CMD_CHIP_SHIFT)); write32(&exynos_drex1->directcmd, - DIRECT_CMD_REFA | (chip << DIRECT_CMD_CHIP_SHIFT)); + DIRECT_CMD_REFA | + (chip << DIRECT_CMD_CHIP_SHIFT)); } } } @@ -324,10 +328,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) * read data fetch cycles and enable DREX auto set powerdown * for input buffer of I/O in none read memory state. */ - write32(&exynos_drex0->concontrol, - mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | DMC_CONCONTROL_IO_PD_CON(0x2)); - write32(&exynos_drex1->concontrol, - mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | DMC_CONCONTROL_IO_PD_CON(0x2)); + write32(&exynos_drex0->concontrol, mem->concontrol | + (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | + DMC_CONCONTROL_IO_PD_CON(0x2)); + write32(&exynos_drex1->concontrol, mem->concontrol | + (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | + DMC_CONCONTROL_IO_PD_CON(0x2)); /* Enable Clock Gating Control for DMC * this saves around 25 mw dmc power as compared to the power diff --git a/src/soc/samsung/exynos5420/usb.c b/src/soc/samsung/exynos5420/usb.c index 9313fea147..c7862232c6 100644 --- a/src/soc/samsung/exynos5420/usb.c +++ b/src/soc/samsung/exynos5420/usb.c @@ -58,12 +58,22 @@ static void setup_dwc3(struct exynos5_usb_drd_dwc3 *dwc3) /* Set relevant registers to default values (clearing all reset bits) */ write32(&dwc3->usb3pipectl, - 0x1 << 24 | 0x4 << 19 | 0x1 << 18 | 0x1 << 17 | 0x1 << 1 | 0); + 0x1 << 24 | /* activate PHY low power states */ + 0x4 << 19 | /* low power delay value */ + 0x1 << 18 | /* activate PHY low power delay */ + 0x1 << 17 | /* enable SuperSpeed PHY suspend */ + 0x1 << 1); /* default Tx deemphasis value */ /* Configure PHY clock turnaround for 8-bit UTMI+, disable suspend */ - write32(&dwc3->usb2phycfg, 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0); + write32(&dwc3->usb2phycfg, + 0x9 << 10 | /* PHY clock turnaround for 8-bit UTMI+ */ + 0x1 << 8 | /* enable PHY sleep in L1 */ + 0x1 << 6); /* enable PHY suspend */ - write32(&dwc3->ctl, 0x5dc << 19 | 0x1 << 16 | 0x1 << 12 | 0); + write32(&dwc3->ctl, + 0x5dc << 19 | /* suspend clock scale for 24MHz */ + 0x1 << 16 | /* retry SS three times (bugfix from U-Boot) */ + 0x1 << 12); /* port capability HOST */ } void setup_usb_drd0_dwc3() @@ -89,13 +99,32 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) write32(&phy->utmi, 1 << 6); write32(&phy->clkrst, - 0x88 << 23 | 0x1 << 20 | 0x1 << 19 | 0x68 << 11 | 0x5 << 5 | 0x1 << 4 | 0x3 << 2 | 0x1 << 1 | 0x1 << 0 | 0); + 0x88 << 23 | /* spread spectrum refclk selector */ + 0x1 << 20 | /* enable spread spectrum */ + 0x1 << 19 | /* enable prescaler refclk */ + 0x68 << 11 | /* multiplier for 24MHz refclk */ + 0x5 << 5 | /* select 24MHz refclk (weird, from U-Boot) */ + 0x1 << 4 | /* power supply in normal operating mode */ + 0x3 << 2 | /* use external refclk (undocumented on 5420?)*/ + 0x1 << 1 | /* force port reset */ + 0x1 << 0); /* normal operating mode */ write32(&phy->param0, - 0x9 << 26 | 0x3 << 22 | 0x1 << 20 | 0x1 << 18 | 0x3 << 13 | 0x3 << 9 | 0x3 << 6 | 0x4 << 3 | 0x4 << 0 | 0); + 0x9 << 26 | /* LOS level */ + 0x3 << 22 | /* TX VREF tune */ + 0x1 << 20 | /* TX rise tune */ + 0x1 << 18 | /* TX res tune */ + 0x3 << 13 | /* TX HS X Vtune */ + 0x3 << 9 | /* TX FS/LS tune */ + 0x3 << 6 | /* SQRX tune */ + 0x4 << 3 | /* OTG tune */ + 0x4 << 0); /* comp disc tune */ write32(&phy->param1, - 0x7f << 19 | 0x7f << 12 | 0x20 << 6 | 0x1c << 0 | 0); + 0x7f << 19 | /* reserved */ + 0x7f << 12 | /* Tx launch amplitude */ + 0x20 << 6 | /* Tx deemphasis 6dB */ + 0x1c << 0); /* Tx deemphasis 3.5dB (value from U-Boot) */ /* disable all test features */ write32(&phy->test, 0);