veyron_rialto: Fix boot failure in romstage.

The FMAP for Rialto has no ecrwhash and would cause verstage to
incorrectly load ramstage (instead of romstage) when looking for
subsection inside RW blob.

We have to override the index of stages to boot correctly.

BRANCH=veyron_rialto
BUG=none
TEST=emerge-veyron_rialto coreboot chromeos-bootimage
     Boots successfully on Rialto boards.

Change-Id: I031703d97a68e42dc17630ab5df85f8cba47e5e5
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 24ba4b16b4a2fe5469296f8d40286ed926cefc3c
Original-Change-Id: I637ea23e1e8265781e52367d1306dbf854c2ccad
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/244577
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9656
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/mainboard/google/veyron_rialto/Kconfig

@@ -49,9 +49,16 @@ config MAINBOARD_VENDOR
 	string
 	default "Google"
 
+# The 'ecrwhash' is removed from FMAP on Rialto, since we don't have EC.
+# As a result, we have to hack RAMSTAGE and ROMSTAGE index until there are
+# better approaches for vboot2 to find right index.
 config VBOOT_RAMSTAGE_INDEX
 	hex
-	default 0x3
+	default 0x2
+
+config VBOOT_ROMSTAGE_INDEX
+	hex
+	default 0x1
 
 config BOOT_MEDIA_SPI_BUS
         int