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mb/pcengines: Enable SuperIO LDN 0xf for GPIO soft reset 

LDN 0xf keeps registers with open-drain configuration of the GPIO.
Enabling the LDN is required for proper GPIO soft reset operation
by the SuperIO driver.

Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ia769e3d8e66015297942bddf328a6fde0bb27ce6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Piotr Kleinschmidt 2020-01-08 15:06:26 +01:00 committed by Felix Held
parent b52f7c7c46
commit 941c9ac074
4 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/pcengines/apu1/devicetree.cb
View File

@ -63,12 +63,12 @@ chip northbridge/amd/agesa/family14/root_complex
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.8 off end device pnp 2e.8 off end
device pnp 2e.f off end
# GPIO0 and GPIO1 are conditionally turned on # GPIO0 and GPIO1 are conditionally turned on
device pnp 2e.007 off end device pnp 2e.007 off end
device pnp 2e.107 off end device pnp 2e.107 off end
device pnp 2e.607 off end device pnp 2e.607 off end
device pnp 2e.e off end device pnp 2e.e off end
device pnp 2e.f on end
end end
chip drivers/pc80/tpm chip drivers/pc80/tpm
device pnp 0c31.0 on end device pnp 0c31.0 on end

2
src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb
View File

@ -65,12 +65,12 @@ chip northbridge/amd/pi/00730F01/root_complex
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.8 off end device pnp 2e.8 off end
device pnp 2e.f off end
# GPIO0 and GPIO1 are conditionally turned on # GPIO0 and GPIO1 are conditionally turned on
device pnp 2e.007 on end device pnp 2e.007 on end
device pnp 2e.107 on end device pnp 2e.107 on end
device pnp 2e.607 off end device pnp 2e.607 off end
device pnp 2e.e off end device pnp 2e.e off end
device pnp 2e.f on end
end # SIO NCT5104D end # SIO NCT5104D
chip drivers/pc80/tpm chip drivers/pc80/tpm
device pnp 0c31.0 on end device pnp 0c31.0 on end

2
src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb
View File

@ -65,12 +65,12 @@ chip northbridge/amd/pi/00730F01/root_complex
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.8 off end device pnp 2e.8 off end
device pnp 2e.f off end
# GPIO0 and GPIO1 are conditionally turned on # GPIO0 and GPIO1 are conditionally turned on
device pnp 2e.007 on end device pnp 2e.007 on end
device pnp 2e.107 on end device pnp 2e.107 on end
device pnp 2e.607 off end device pnp 2e.607 off end
device pnp 2e.e off end device pnp 2e.e off end
device pnp 2e.f on end
end # SIO NCT5104D end # SIO NCT5104D
end # LPC 0x439d end # LPC 0x439d

2
src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb
View File

@ -65,12 +65,12 @@ chip northbridge/amd/pi/00730F01/root_complex
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.8 off end device pnp 2e.8 off end
device pnp 2e.f off end
# GPIO0 and GPIO1 are conditionally turned on # GPIO0 and GPIO1 are conditionally turned on
device pnp 2e.007 on end device pnp 2e.007 on end
device pnp 2e.107 on end device pnp 2e.107 on end
device pnp 2e.607 off end device pnp 2e.607 off end
device pnp 2e.e off end device pnp 2e.e off end
device pnp 2e.f on end
end # SIO NCT5104D end # SIO NCT5104D
end # LPC 0x439d end # LPC 0x439d