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samsung/exynos5: add resource functions for the display port 

This does NOT turn on the graphics.

The device tree has been changed enough so that, at the very least, the correct
functions are called at the correct time, with the correct paramaters. We
decided to yank the I2C entries as they did not obvious function and might
not even have been correct.

Not working, seemingly, but we need to add a 4M resource for
memory, and it seems it needs to be fixed at the address shown.
This address was chosen from current hardware.

We realized that the display code should be part of the cpu -- that's how
the hardware works!

Change-Id: Ied65a554f833566be817540702f79a02e7b6cb6e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2615
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Ronald G. Minnich 2013-03-18 09:49:54 -07:00 committed by David Hendricks
parent f9be756b55
commit 9427ca151e
7 changed files with 102 additions and 143 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/samsung/exynos5-common/displayport/Kconfig
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@ -1,2 +0,0 @@
config EXYNOS_DISPLAYPORT
bool

2
src/cpu/samsung/exynos5-common/displayport/Makefile.inc
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@ -1,2 +0,0 @@
ramstage-$(CONFIG_EXYNOS_DISPLAYPORT) += displayport.c

107
src/cpu/samsung/exynos5-common/displayport/displayport.c
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@ -1,107 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdlib.h>
#include <string.h>
#include <delay.h>
#include <arch/io.h>
#include <device/device.h>
/* we distinguish a display port device from a raw graphics device because there are
* dramatic differences in startup depending on graphics usage. To make startup fast
* and easier to understand and debug we explicitly name this common case. The alternate
* approach, involving lots of machine and callbacks, is hard to debug and verify.
*/
static void exynos_displayport_init(void)
{
struct cpu_samsung_exynos5_common_displayport_config *conf = dev->chip_info;
/* put these on the stack. If, at some point, we want to move this code to a
* pre-ram stage, it will be much easier.
*/
vidinfo_t vi;
struct exynos5_fimd_panel panel;
void *lcdbase;
memset(vi, 0, sizeof(vi));
memset(panel, 0, sizeof(panel));
panel.is_dp = 1; /* Display I/F is eDP */
/* while it is true that we did a memset to zero,
* we leave some 'set to zero' entries here to make
* it clear what's going on. Graphics is confusing.
*/
panel.is_mipi = 0;
panel.fixvclk = 0;
panel.ivclk = 0;
panel.clkval_f = conf->clkval_f;
panel.upper_margin = conf->upper_margin;
panel.lower_margin = conf->lower_margin;
panel.vsync = conf->vsync;
panel.left_margin = conf->left_margin;
panel.right_margin = conf->right_margin;
panel.hsync = conf->hsync;
vi->vl_col = conf->xres;
vi->fl_row = conf->yres;
vi->vl_bpix = conf->bpp;
vi->cmap = cbmem_reserve(64*1024); /* The size is a magic number from hardware. */
lcdbase = conf->lcdbase;
printk(BIOS_DEBUG, "Initializing exynos VGA\n");
ret = lcd_ctrl_init(&vi, &panel, lcdbase);
#if 0
ret = board_dp_lcd_vdd(blob, &wait_ms);
ret = board_dp_bridge_setup(blob, &wait_ms);
while (tries < 5) {
ret = board_dp_bridge_init(blob, &wait_ms);
ret = board_dp_hotplug(blob, &wait_ms);
if (ret) {
ret = board_dp_bridge_reset(blob, &wait_ms);
continue;
}
ret = dp_controller_init(blob, &wait_ms);
ret = board_dp_backlight_vdd(blob, &wait_ms);
ret = board_dp_backlight_pwm(blob, &wait_ms);
ret = board_dp_backlight_en(blob, &wait_ms);
}
#endif
}
static void exynos_displayport_noop(device_t dummy)
{
}
static struct device_operations exynos_displayport_operations = {
.read_resources = exynos_displayport_noop,
.set_resources = exynos_displayport_noop,
.enable_resources = exynos_displayport_noop,
.init = exynos_displayport_init,
.scan_bus = exynos_displayport_noop,
};
static void exynos_displayport_enable(struct device *dev)
{
if (dev->link_list != NULL)
dev->ops = &exynos_displayport_operations;
}
struct chip_operations drivers_i2c_exynos_displayport_ops = {
CHIP_NAME("exynos displayport")
.enable_dev = exynos_displayport_enable;
};

4
src/cpu/samsung/exynos5-common/exynos-fb.c
View File

@ -100,7 +100,7 @@ static void fimd_bypass(void)
{ {
struct exynos5_sysreg *sysreg = samsung_get_base_sysreg(); struct exynos5_sysreg *sysreg = samsung_get_base_sysreg();
/*setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);*/ setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);
sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1; sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1;
} }
@ -586,7 +586,9 @@ int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data,
//vi->yres = panel_info->vl_row; //vi->yres = panel_info->vl_row;
fimd_bypass(); fimd_bypass();
printk(BIOS_SPEW, "fimd_bypass\n");
fb_init(panel_info, lcdbase, panel_data); fb_init(panel_info, lcdbase, panel_data);
printk(BIOS_SPEW, "fb_init(%p, %p, %p\n",panel_info, lcdbase, panel_data);
/* Enable flushing after LCD writes if requested */ /* Enable flushing after LCD writes if requested */
// forget it. lcd_set_flush_dcache(1); // forget it. lcd_set_flush_dcache(1);

8
src/cpu/samsung/exynos5-common/displayport/chip.h → src/cpu/samsung/exynos5250/chip.h
View File

@ -17,10 +17,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#ifndef CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H #ifndef CPU_SAMSUNG_EXYNOS5250_H
#define CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H #define CPU_SAMSUNG_EXYNOS5250_H
struct cpu_samsung_exynos5_common_displayport_config { struct cpu_samsung_exynos5250_config {
/* special magic numbers! */ /* special magic numbers! */
int clkval_f; int clkval_f;
int upper_margin; int upper_margin;
@ -37,4 +37,4 @@ struct cpu_samsung_exynos5_common_displayport_config {
u32 lcdbase; u32 lcdbase;
}; };
#endif /* CPU_SAMSUNG_EXYNOS5-COMMON_DISPLAYPORT_H */ #endif /* CPU_SAMSUNG_EXYNOS5250_H */

84
src/cpu/samsung/exynos5250/cpu.c
View File

@ -1,5 +1,14 @@
#include <stdlib.h>
#include <string.h>
#include <stddef.h>
#include <delay.h>
#include <console/console.h> #include <console/console.h>
#include <arch/io.h>
#include <device/device.h> #include <device/device.h>
#include <cbmem.h>
#include <cpu/samsung/exynos5250/fimd.h>
#include <cpu/samsung/exynos5-common/s5p-dp-core.h>
#include "chip.h"
#define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10)
#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL)
@ -28,8 +37,76 @@ static struct device_operations domain_ops = {
.scan_bus = domain_scan_bus, .scan_bus = domain_scan_bus,
}; };
/* we distinguish a display port device from a raw graphics device because there are
* dramatic differences in startup depending on graphics usage. To make startup fast
* and easier to understand and debug we explicitly name this common case. The alternate
* approach, involving lots of machine and callbacks, is hard to debug and verify.
*/
static void exynos_displayport_init(device_t dev)
{
int ret;
struct cpu_samsung_exynos5250_config *conf = dev->chip_info;
/* put these on the stack. If, at some point, we want to move this code to a
* pre-ram stage, it will be much easier.
*/
vidinfo_t vi;
struct exynos5_fimd_panel panel;
u32 lcdbase;
printk(BIOS_SPEW, "%s: dev %p, conf %p\n", __func__, dev, conf);
memset(&vi, 0, sizeof(vi));
memset(&panel, 0, sizeof(panel));
panel.is_dp = 1; /* Display I/F is eDP */
/* while it is true that we did a memset to zero,
* we leave some 'set to zero' entries here to make
* it clear what's going on. Graphics is confusing.
*/
panel.is_mipi = 0;
panel.fixvclk = 0;
panel.ivclk = 0;
panel.clkval_f = conf->clkval_f;
panel.upper_margin = conf->upper_margin;
panel.lower_margin = conf->lower_margin;
panel.vsync = conf->vsync;
panel.left_margin = conf->left_margin;
panel.right_margin = conf->right_margin;
panel.hsync = conf->hsync;
vi.vl_col = conf->xres;
vi.vl_row = conf->yres;
vi.vl_bpix = conf->bpp;
printk(BIOS_SPEW, "lcd base is %p\n", (void *)(conf->lcdbase));
/* The size is a magic number from hardware. */
mmio_resource(dev, 0, conf->lcdbase/KiB, 64);
vi.cmap = (void *)conf->lcdbase;
lcdbase = conf->lcdbase + 64*KiB;
mmio_resource(dev, 1, lcdbase, (conf->xres*conf->yres*4 + (KiB-1))/KiB);
printk(BIOS_DEBUG, "Initializing exynos VGA, base %p\n",(void *)lcdbase);
ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase);
#if 0
ret = board_dp_lcd_vdd(blob, &wait_ms);
ret = board_dp_bridge_setup(blob, &wait_ms);
while (tries < 5) {
ret = board_dp_bridge_init(blob, &wait_ms);
ret = board_dp_hotplug(blob, &wait_ms);
if (ret) {
ret = board_dp_bridge_reset(blob, &wait_ms);
continue;
}
ret = dp_controller_init(blob, &wait_ms);
ret = board_dp_backlight_vdd(blob, &wait_ms);
ret = board_dp_backlight_pwm(blob, &wait_ms);
ret = board_dp_backlight_en(blob, &wait_ms);
}
#endif
}
static void cpu_init(device_t dev) static void cpu_init(device_t dev)
{ {
printk(BIOS_SPEW, "%s\n", __func__);
exynos_displayport_init(dev);
} }
static void cpu_noop(device_t dev) static void cpu_noop(device_t dev)
@ -44,17 +121,20 @@ static struct device_operations cpu_ops = {
.scan_bus = 0, .scan_bus = 0,
}; };
static void enable_dev(device_t dev) static void enable_exynos5250_dev(device_t dev)
{ {
/* Set the operations if it is a special bus type */ /* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) { if (dev->path.type == DEVICE_PATH_DOMAIN) {
printk(BIOS_SPEW, "%s: DOMAIN\n", __func__);
dev->ops = &domain_ops; dev->ops = &domain_ops;
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
printk(BIOS_SPEW, "%s: CPU_CLUSTER\n", __func__);
dev->ops = &cpu_ops; dev->ops = &cpu_ops;
} }
printk(BIOS_SPEW, "%s: done\n", __func__);
} }
struct chip_operations cpu_samsung_exynos5250_ops = { struct chip_operations cpu_samsung_exynos5250_ops = {
CHIP_NAME("CPU Samsung Exynos 5250") CHIP_NAME("CPU Samsung Exynos 5250")
.enable_dev = enable_dev, .enable_dev = enable_exynos5250_dev,
}; };

38
src/mainboard/google/snow/devicetree.cb
View File

@ -17,30 +17,18 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
# FIXME: this is just a stub for now
chip cpu/samsung/exynos5250 chip cpu/samsung/exynos5250
device cpu_cluster 0 on end
device cpu_cluster 0 on register "xres" = "1366"
end register "yres" = "768"
register "bpp" = "16"
device domain 0 on # complex magic timing!
chip drivers/generic/generic # I2C0 controller register "clkval_f" = "2"
device i2c 6 on end # ? register "upper_margin" = "14"
device i2c 9 on end # ? register "lower_margin" = "3"
end register "vsync" = "5"
chip cpu/samsung/exynos5-common/displayport register "left_margin" = "80"
register "xres" = "1366" register "right_margin" = "48"
register "yres" = "768" register "hsync" = "32"
register "bpp" = "16" register "lcdbase" = "0x50000000"
# complex magic timing!
register "clkval_f" = "2"
register "upper_margin" = "14"
register "lower_margin" = "3"
register "vsync" = "5"
register "left_margin" = "80"
register "right_margin" = "48"
register "hsync" = "32"
register "lcdbase" = "0x10000000"
end
end
end end