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Tyan update for ROM_IMAGE_SIZE > 64K

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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu 2004-11-02 02:34:28 +00:00
parent 0979969732
commit 9434c1b661
38 changed files with 356 additions and 219 deletions
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39
src/mainboard/tyan/s2850/Config.lb
View file

@ -47,22 +47,22 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h "
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
@ -162,14 +162,21 @@ chip northbridge/amd/amdk8
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x201
io 0x62 = 0x330
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on end

14
src/mainboard/tyan/s2850/Options.lb
View file

@ -32,6 +32,8 @@ uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
@ -43,7 +45,8 @@ uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
###
### Build options
@ -80,7 +83,7 @@ default HARD_RESET_FUNCTION=0
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=9
default IRQ_SLOT_COUNT=12
##
## Build code to export an x86 MP table
@ -117,6 +120,8 @@ default CONFIG_IOAPIC=1
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s2850"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2850
###
### LinuxBIOS layout values
@ -160,6 +165,11 @@ default CONFIG_ROM_STREAM = 1
default CC="gcc"
default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
##
## The Serial Console
##

4
src/mainboard/tyan/s2850/auto.c
View file

@ -111,7 +111,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
//#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
@ -144,7 +144,7 @@ static void main(unsigned long bist)
init_timer();
if (cpu_init_detected()) {
#if 0
#if 1
asm volatile ("jmp __cpu_reset");
#else
/* cpu reset also reset the memtroller ????

1
src/mainboard/tyan/s2850/mainboard.c
View file

@ -269,6 +269,5 @@ static void enable_dev(struct device *dev)
dev_root.ops = &mainboard_operations;
}
struct chip_operations mainboard_tyan_s2850_ops = {
.name = "Tyan s2850 mainboard ",
.enable_dev = enable_dev,
};

40
src/mainboard/tyan/s2875/Config.lb
View file

@ -43,26 +43,27 @@ if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h "
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
@ -167,14 +168,21 @@ chip northbridge/amd/amdk8
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x201
io 0x62 = 0x330
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on end

13
src/mainboard/tyan/s2875/Options.lb
View file

@ -32,6 +32,8 @@ uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
@ -43,6 +45,8 @@ uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
###
@ -80,7 +84,7 @@ default HARD_RESET_FUNCTION=0
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=9
default IRQ_SLOT_COUNT=13
##
## Build code to export an x86 MP table
@ -117,6 +121,8 @@ default CONFIG_IOAPIC=1
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s2875"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2875
###
### LinuxBIOS layout values
@ -160,6 +166,11 @@ default CONFIG_ROM_STREAM = 1
default CC="gcc"
default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
##
## The Serial Console
##

4
src/mainboard/tyan/s2875/auto.c
View file

@ -128,7 +128,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
//#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
@ -173,7 +173,7 @@ static void main(unsigned long bist)
init_timer();
if (cpu_init_detected()) {
#if 0
#if 1
asm volatile ("jmp __cpu_reset");
#else
/* cpu reset also reset the memtroller ????

1
src/mainboard/tyan/s2875/mainboard.c
View file

@ -269,6 +269,5 @@ static void enable_dev(struct device *dev)
dev_root.ops = &mainboard_operations;
}
struct chip_operations mainboard_tyan_s2875_ops = {
.name = "Tyan s2875 mainboard ",
.enable_dev = enable_dev,
};

40
src/mainboard/tyan/s2880/Config.lb
View file

@ -43,26 +43,27 @@ if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h "
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
@ -169,14 +170,21 @@ chip northbridge/amd/amdk8
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x201
io 0x62 = 0x330
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on end

15
src/mainboard/tyan/s2880/Options.lb
View file

@ -32,6 +32,8 @@ uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
@ -43,6 +45,8 @@ uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
###
@ -80,7 +84,7 @@ default HARD_RESET_FUNCTION=0
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=9
default IRQ_SLOT_COUNT=13
##
## Build code to export an x86 MP table
@ -116,7 +120,9 @@ default CONFIG_IOAPIC=1
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s2881"
default MAINBOARD_VENDOR="s2880"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880
###
### LinuxBIOS layout values
@ -160,6 +166,11 @@ default CONFIG_ROM_STREAM = 1
default CC="gcc"
default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
##
## The Serial Console
##

4
src/mainboard/tyan/s2880/auto.c
View file

@ -123,7 +123,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
//#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
@ -168,7 +168,7 @@ static void main(unsigned long bist)
init_timer();
if (cpu_init_detected()) {
#if 0
#if 1
asm volatile ("jmp __cpu_reset");
#else
/* cpu reset also reset the memtroller ????

1
src/mainboard/tyan/s2880/mainboard.c
View file

@ -269,6 +269,5 @@ static void enable_dev(struct device *dev)
dev_root.ops = &mainboard_operations;
}
struct chip_operations mainboard_tyan_s2880_ops = {
.name = "Tyan s2880 mainboard ",
.enable_dev = enable_dev,
};

40
src/mainboard/tyan/s2881/Config.lb
View file

@ -43,26 +43,27 @@ if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h "
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
@ -171,14 +172,21 @@ chip northbridge/amd/amdk8
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x201
io 0x62 = 0x330
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on end

11
src/mainboard/tyan/s2881/Options.lb
View file

@ -32,6 +32,8 @@ uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
@ -43,6 +45,8 @@ uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
###
@ -117,6 +121,8 @@ default CONFIG_IOAPIC=1
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s2881"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881
###
### LinuxBIOS layout values
@ -160,6 +166,11 @@ default CONFIG_ROM_STREAM = 1
default CC="gcc"
default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
##
## The Serial Console
##

7
src/mainboard/tyan/s2881/auto.c
View file

@ -123,12 +123,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
//#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c" /* tyan does not want the default */
/* tyan does not want the default */
#include "resourcemap.c"
#define FIRST_CPU 1
#define SECOND_CPU 1
@ -167,7 +168,7 @@ static void main(unsigned long bist)
init_timer();
if (cpu_init_detected()) {
#if 0
#if 1
asm volatile ("jmp __cpu_reset");
#else
/* cpu reset also reset the memtroller ????

1
src/mainboard/tyan/s2881/mainboard.c
View file

@ -269,6 +269,5 @@ static void enable_dev(struct device *dev)
dev_root.ops = &mainboard_operations;
}
struct chip_operations mainboard_tyan_s2881_ops = {
.name = "Tyan s2881 mainboard ",
.enable_dev = enable_dev,
};

39
src/mainboard/tyan/s2882/Config.lb
View file

@ -47,22 +47,22 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h "
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
@ -169,14 +169,21 @@ chip northbridge/amd/amdk8
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x201
io 0x62 = 0x330
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on end

15
src/mainboard/tyan/s2882/Options.lb
View file

@ -32,6 +32,8 @@ uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
@ -43,6 +45,8 @@ uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
###
@ -80,7 +84,7 @@ default HARD_RESET_FUNCTION=0
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=9
default IRQ_SLOT_COUNT=15
##
## Build code to export an x86 MP table
@ -117,6 +121,8 @@ default CONFIG_IOAPIC=1
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s2882"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882
###
### LinuxBIOS layout values
@ -160,6 +166,11 @@ default CONFIG_ROM_STREAM = 1
default CC="gcc"
default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
##
## The Serial Console
##
@ -198,7 +209,7 @@ default TTYS0_LCS=0x3
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=8
default DEFAULT_CONSOLE_LOGLEVEL=7
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=8

6
src/mainboard/tyan/s2882/auto.c
View file

@ -126,12 +126,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
//#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/resourcemap.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "northbridge/amd/amdk8/resourcemap.c"
#define FIRST_CPU 1
#define SECOND_CPU 1
@ -176,7 +176,7 @@ static void main(unsigned long bist)
init_timer();
if (cpu_init_detected()) {
#if 0
#if 1
asm volatile ("jmp __cpu_reset");
#else
/* cpu reset also reset the memtroller ????

1
src/mainboard/tyan/s2882/mainboard.c
View file

@ -269,6 +269,5 @@ static void enable_dev(struct device *dev)
dev_root.ops = &mainboard_operations;
}
struct chip_operations mainboard_tyan_s2882_ops = {
.name = "Tyan s2882 mainboard ",
.enable_dev = enable_dev,
};

21
src/mainboard/tyan/s2885/Config.lb
View file

@ -43,26 +43,27 @@ if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h "
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
@ -199,8 +200,8 @@ chip northbridge/amd/amdk8
device pci 1.3 on end
device pci 1.5 on end
device pci 1.6 off end
# register "ide0_enable" = "1"
# register "ide1_enable" = "1"
register "ide0_enable" = "1"
register "ide1_enable" = "1"
end
end # device pci 18.0

9
src/mainboard/tyan/s2885/Options.lb
View file

@ -45,6 +45,8 @@ uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
###
@ -82,7 +84,7 @@ default HARD_RESET_FUNCTION=0
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=9
default IRQ_SLOT_COUNT=11
##
## Build code to export an x86 MP table
@ -164,6 +166,11 @@ default CONFIG_ROM_STREAM = 1
default CC="gcc"
default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
##
## The Serial Console
##

13
src/mainboard/tyan/s2885/auto.c
View file

@ -56,28 +56,22 @@ static void soft2_reset(void)
static void memreset_setup(void)
{
#if 0
if (is_cpu_pre_c0()) {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
}
else {
#endif
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
#if 0
}
#endif
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
#if 0
if (is_cpu_pre_c0()) {
udelay(800);
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
#endif
}
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
@ -123,7 +117,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
};
if(maxnodes>2) {
// print_debug("this mainboard is only designed for 2 cpus\r\n");
print_debug("this mainboard is only designed for 2 cpus\r\n");
maxnodes=2;
}
@ -150,7 +144,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c" /* tyan does not want the default */
/* tyan does not want the default */
#include "resourcemap.c"
#define FIRST_CPU 1
#define SECOND_CPU 1
@ -205,7 +200,7 @@ static void main(unsigned long bist)
init_timer();
if (cpu_init_detected()) {
#if 0
#if 1
asm volatile ("jmp __cpu_reset");
#else
/* cpu reset also reset the memtroller ????

1
src/mainboard/tyan/s2885/mainboard.c
View file

@ -269,6 +269,5 @@ static void enable_dev(struct device *dev)
dev_root.ops = &mainboard_operations;
}
struct chip_operations mainboard_tyan_s2885_ops = {
.name = "Tyan s2885 mainboard ",
.enable_dev = enable_dev,
};

57
src/mainboard/tyan/s2885/mptable.c
View file

@ -13,10 +13,12 @@ void *smp_write_config_table(void *v)
unsigned char bus_num;
unsigned char bus_isa;
unsigned char bus_8131_0;
unsigned char bus_8131_1;
unsigned char bus_8131_2;
unsigned char bus_8111_0;
unsigned char bus_8111_1;
unsigned char bus_8151_0;
unsigned char bus_8151_1;
@ -42,56 +44,59 @@ void *smp_write_config_table(void *v)
{
device_t dev;
/* 8111 */
dev = dev_find_slot(3, PCI_DEVFN(0x03,0));
/* 8151 */
bus_8151_0 = 1;
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
if (dev) {
bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
// printk_debug("bus_8151_1=%d\n",bus_8151_1);
bus_8111_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_8111_0++;
bus_8131_0 = bus_8111_0;
// printk_debug("bus_8111_0=%d\n",bus_8111_0);
}
else {
printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
bus_8151_1 = 2;
bus_8111_0 = bus_8131_0 = 3;
}
/* 8111 */
dev = dev_find_slot(bus_8111_0, PCI_DEVFN(0x03,0));
if (dev) {
bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
printk_debug("bus_isa=%d\n",bus_isa);
// printk_debug("bus_isa=%d\n",bus_isa);
}
else {
printk_debug("ERROR - could not find PCI 3:03.0, using defaults\n");
printk_debug("ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
bus_8111_1 = 6;
bus_isa = 7;
}
/* 8131-1 */
dev = dev_find_slot(3, PCI_DEVFN(0x01,0));
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x01,0));
if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk_debug("ERROR - could not find PCI 3:01.0, using defaults\n");
printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
bus_8131_1 = 4;
}
/* 8131-2 */
dev = dev_find_slot(3, PCI_DEVFN(0x02,0));
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x02,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk_debug("ERROR - could not find PCI 3:02.0, using defaults\n");
printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
bus_8131_2 = 5;
}
/* 8151 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
if (dev) {
bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
printk_debug("bus_8151_1=%d\n",bus_8151_1);
}
else {
printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
bus_8151_1 = 2;
}
}
@ -105,18 +110,18 @@ void *smp_write_config_table(void *v)
smp_write_bus(mc, bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
smp_write_ioapic(mc, 2, 0x11, 0xfec00000); //8111
{
device_t dev;
struct resource *res;
dev = dev_find_slot(3, PCI_DEVFN(0x1,1));
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x03, 0x11, res->base);
smp_write_ioapic(mc, 3, 0x11, res->base);
}
}
dev = dev_find_slot(3, PCI_DEVFN(0x2,1));
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x2,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {

39
src/mainboard/tyan/s4880/Config.lb
View file

@ -47,22 +47,22 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h"
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
@ -171,14 +171,21 @@ chip northbridge/amd/amdk8
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x201
io 0x62 = 0x330
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on end

13
src/mainboard/tyan/s4880/Options.lb
View file

@ -32,6 +32,8 @@ uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
@ -43,6 +45,8 @@ uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
###
@ -80,7 +84,7 @@ default HARD_RESET_FUNCTION=0
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=9
default IRQ_SLOT_COUNT=22
##
## Build code to export an x86 MP table
@ -117,6 +121,8 @@ default CONFIG_IOAPIC=1
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s4880"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4880
###
### LinuxBIOS layout values
@ -160,6 +166,11 @@ default CONFIG_ROM_STREAM = 1
default CC="gcc"
default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
##
## The Serial Console
##

7
src/mainboard/tyan/s4880/auto.c
View file

@ -147,13 +147,14 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
//#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c" /* tyan does not want the default */
/* tyan does not want the default */
#include "resourcemap.c"
#define FIRST_CPU 1
#define SECOND_CPU 1
@ -235,7 +236,7 @@ static void main(unsigned long bist)
init_timer();
if (cpu_init_detected()) {
#if 0
#if 1
asm volatile ("jmp __cpu_reset");
#else
/* cpu reset also reset the memtroller ????

1
src/mainboard/tyan/s4880/mainboard.c
View file

@ -269,6 +269,5 @@ static void enable_dev(struct device *dev)
dev_root.ops = &mainboard_operations;
}
struct chip_operations mainboard_tyan_s4880_ops = {
.name = "Tyan s4880 mainboard ",
.enable_dev = enable_dev,
};

4
src/mainboard/tyan/s4880/mptable.c
View file

@ -134,8 +134,8 @@ void *smp_write_config_table(void *v)
//On Board Via USB 1.1 and 2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|0, 0x4, 0x11); //1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|1, 0x4, 0x12); //1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|2, 0x4, 0x10); //2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|1, 0x4, 0x10); //1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|2, 0x4, 0x12); //2
//Slot 5 PCI 32
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, 0x4, 0x10);

39
src/mainboard/tyan/s4882/Config.lb
View file

@ -47,22 +47,22 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h "
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
@ -170,14 +170,21 @@ chip northbridge/amd/amdk8
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x201
io 0x62 = 0x330
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on end

13
src/mainboard/tyan/s4882/Options.lb
View file

@ -32,6 +32,8 @@ uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CC
@ -43,6 +45,8 @@ uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
###
@ -80,7 +84,7 @@ default HARD_RESET_FUNCTION=0
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=9
default IRQ_SLOT_COUNT=22
##
## Build code to export an x86 MP table
@ -117,6 +121,8 @@ default CONFIG_IOAPIC=1
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s4882"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882
###
### LinuxBIOS layout values
@ -160,6 +166,11 @@ default CONFIG_ROM_STREAM = 1
default CC="gcc"
default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
##
## The Serial Console
##

7
src/mainboard/tyan/s4882/auto.c
View file

@ -147,13 +147,14 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
//#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c" /* tyan does not want the default */
/* tyan does not want the default */
#include "resourcemap.c"
#define FIRST_CPU 1
#define SECOND_CPU 1
@ -234,7 +235,7 @@ static void main(unsigned long bist)
init_timer();
if (cpu_init_detected()) {
#if 0
#if 1
asm volatile ("jmp __cpu_reset");
#else
/* cpu reset also reset the memtroller ????

1
src/mainboard/tyan/s4882/mainboard.c
View file

@ -269,6 +269,5 @@ static void enable_dev(struct device *dev)
dev_root.ops = &mainboard_operations;
}
struct chip_operations mainboard_tyan_s4882_ops = {
.name = "Tyan s4882 mainboard ",
.enable_dev = enable_dev,
};

4
src/mainboard/tyan/s4882/mptable.c
View file

@ -134,8 +134,8 @@ void *smp_write_config_table(void *v)
//On Board Via USB 1.1 and 2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|0, 0x4, 0x11); //1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|1, 0x4, 0x12); //1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|2, 0x4, 0x10); //2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|1, 0x4, 0x10); //1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|2, 0x4, 0x12); //2
//Slot 5 PCI 32
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, 0x4, 0x10);

6
targets/tyan/s2885/Config.lb
View file

@ -14,7 +14,8 @@ romimage "normal"
# 64K for Etherboot
# option ROM_SIZE = 458752
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
option ROM_IMAGE_SIZE=0x10400
option XIP_ROM_SIZE=0x20000
option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@ -28,7 +29,8 @@ end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option ROM_IMAGE_SIZE=0x10400
option XIP_ROM_SIZE=0x20000
option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf

6
targets/tyan/s4880/Config.lb
View file

@ -14,7 +14,8 @@ romimage "normal"
# 64K for Etherboot
# option ROM_SIZE = 458752
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
option ROM_IMAGE_SIZE=0x11800
option XIP_ROM_SIZE=0x20000
option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@ -28,7 +29,8 @@ end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option ROM_IMAGE_SIZE=0x11800
option XIP_ROM_SIZE=0x20000
option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf

6
targets/tyan/s4882/Config.lb
View file

@ -14,7 +14,8 @@ romimage "normal"
# 64K for Etherboot
# option ROM_SIZE = 458752
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
option ROM_IMAGE_SIZE=0x11800
option XIP_ROM_SIZE=0x20000
option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@ -28,7 +29,8 @@ end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option ROM_IMAGE_SIZE=0x11800
option XIP_ROM_SIZE=0x20000
option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf