From 944655dadaf595bf655f266eb35ca2f17c8410eb Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Wed, 18 May 2016 10:26:53 -0700 Subject: [PATCH] soc/apollolake: Use simpler macros for the northbridge PCI device The NB_DEV_ROOT macro, is almost unreadable, as it depends on other stringified macros, and acts differently depending on the coreboot stage. For ramstage, it also hides a function call. Rewrite the macro in terms of more basic and readable macros. Change-Id: I9b7071d67c8d58926e9b01fadaa239db1120448c Signed-off-by: Alexandru Gagniuc Reviewed-on: https://review.coreboot.org/14890 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/chip.c | 2 +- src/soc/intel/apollolake/include/soc/pci_devs.h | 12 +++--------- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 610faa8273..d7c61c14dc 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -100,7 +100,7 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) /* Load VBT before devicetree-specific config. */ silconfig->GraphicsConfigPtr = (uintptr_t)vbt; - struct device *dev = NB_DEV_ROOT; + struct device *dev = dev_find_slot(NB_BUS, NB_DEVFN); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index ec550e8810..d11b9a7172 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -17,26 +17,17 @@ #include -#define _NB_DEVFN(slot) PCI_DEVFN(NB_DEV_SLOT_ ## slot, 0) #define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func) - #if !defined(__SIMPLE_DEVICE__) #include #include -#define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot)) #define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func)) #else #include -#define _NB_DEV(slot) PCI_DEV(0, NB_DEV_SLOT_ ## slot, 0) #define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func) #endif -/* North bridge devices */ -#define NB_DEV_SLOT_ROOT 0x00 -#define NB_DEVFN_ROOT _NB_DEVFN(ROOT) -#define NB_DEV_ROOT _NB_DEV(ROOT) - /* LPSS UART */ #define LPSS_DEV_SLOT_UART 0x18 #define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0) @@ -48,6 +39,9 @@ #define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2) #define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3) +#define NB_BUS 0 +#define NB_DEVFN PCI_DEVFN(0, 0) +#define NB_DEV_ROOT PCI_DEV(NB_BUS, 0x0, 0) #define P2SB_DEV PCI_DEV(0, 0xd, 0) #define PMC_DEV PCI_DEV(0, 0xd, 1) #define SPI_DEV PCI_DEV(0, 0xd, 2)