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util/inteltool: Add Apollo Lake LPC ID and allow to read PCRs 

The P2SB (PCI to Side-Band) bridge is on a different PCI device on APL.
Hence, we have to decide based on the LPC ID which device to query.

Also fix a comment.

Change-Id: Ie20d7d2d246629d085bcf4740ba28b1e81e6a12a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29896
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber 2018-11-20 12:10:29 +01:00 committed by Nico Huber
parent b59da487e1
commit 94473afcd2
3 changed files with 31 additions and 3 deletions
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1
util/inteltool/inteltool.c
View File

@ -247,6 +247,7 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224, "C224"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224, "C224"},
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, "C226"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, "C226"},
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"},
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" },
/* Intel GPUs */ /* Intel GPUs */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS,
"Intel(R) G35 Express Chipset Family" }, "Intel(R) G35 Express Chipset Family" },

2
util/inteltool/inteltool.h
View File

@ -227,6 +227,8 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31
#define CPUID_BAYTRAIL 0x30670 #define CPUID_BAYTRAIL 0x30670
#define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8
/* Intel starts counting these generations with the integration of the DRAM controller */ /* Intel starts counting these generations with the integration of the DRAM controller */
#define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */ #define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */
#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */ #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */

31
util/inteltool/pcr.c
View File

@ -70,11 +70,36 @@ void pcr_init(struct pci_dev *const sb)
{ {
bool error_exit = false; bool error_exit = false;
bool p2sb_revealed = false; bool p2sb_revealed = false;
struct pci_dev *p2sb;
if (sbbar) if (sbbar)
return; return;
struct pci_dev *const p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1); switch (sb->device_id) {
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE:
case PCI_DEVICE_ID_INTEL_H110:
case PCI_DEVICE_ID_INTEL_H170:
case PCI_DEVICE_ID_INTEL_Z170:
case PCI_DEVICE_ID_INTEL_Q170:
case PCI_DEVICE_ID_INTEL_Q150:
case PCI_DEVICE_ID_INTEL_B150:
case PCI_DEVICE_ID_INTEL_C236:
case PCI_DEVICE_ID_INTEL_C232:
case PCI_DEVICE_ID_INTEL_QM170:
case PCI_DEVICE_ID_INTEL_HM170:
case PCI_DEVICE_ID_INTEL_CM236:
case PCI_DEVICE_ID_INTEL_HM175:
case PCI_DEVICE_ID_INTEL_QM175:
case PCI_DEVICE_ID_INTEL_CM238:
p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1);
break;
case PCI_DEVICE_ID_INTEL_APL_LPC:
p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0);
break;
default:
perror("Unknown LPC device.");
exit(1);
}
if (!p2sb) { if (!p2sb) {
perror("Can't allocate device node for P2SB."); perror("Can't allocate device node for P2SB.");
@ -86,8 +111,8 @@ void pcr_init(struct pci_dev *const sb)
if (p2sb->vendor_id == 0xffff && p2sb->device_id == 0xffff) { if (p2sb->vendor_id == 0xffff && p2sb->device_id == 0xffff) {
printf("Trying to reveal Primary to Sideband Bridge " printf("Trying to reveal Primary to Sideband Bridge "
"(P2SB),\nlet's hope the OS doesn't mind... "); "(P2SB),\nlet's hope the OS doesn't mind... ");
/* Do not use pci_write_long(). Surrounding /* Do not use pci_write_long(). Bytes
bytes 0xe0 must be maintained. */ surrounding 0xe0 must be maintained. */
pci_write_byte(p2sb, 0xe0 + 1, 0); pci_write_byte(p2sb, 0xe0 + 1, 0);
pci_fill_info(p2sb, PCI_FILL_IDENT | PCI_FILL_RESCAN); pci_fill_info(p2sb, PCI_FILL_IDENT | PCI_FILL_RESCAN);