soc/mediatek/mt8183: Pass MR values as function arguments
To make data flow more explicit, global variables 'MR01Value' and
'MR13Value' are replaced with local variables, which are passed as
function arguments.
BRANCH=kukui
BUG=none
TEST=1. emerge-kukui coreboot
2. Fast calibration succeeded
Change-Id: Id21483092c86c3ae7dbb1173a2b943defe41a379
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Yu-Ping Wu
Patrick Georgi
parent
845652b8bb
commit
947916eb2d
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@ -739,24 +739,24 @@ static u8 dramc_zq_calibration(u8 chn, u8 rank)
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return 0;
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}
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u8 MR01Value[FSP_MAX] = {0x26, 0x56};
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u8 MR13Value = (1 << 4) | (1 << 3);
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static void dramc_mode_reg_init(u8 freq_group)
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static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr)
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{
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u8 *MR01Value = mr->MR01Value;
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u8 MR02Value[FSP_MAX] = {0x12, 0x12};
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u8 MR03Value = 0x30;
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u8 MR11Value[FSP_MAX] = {0x0, 0x23};
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u8 MR12Value[CHANNEL_MAX][RANK_MAX][FSP_MAX] = {
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{{0x5d, 0x5d}, {0x5d, 0x5d} }, {{0x5d, 0x5d}, {0x5d, 0x5d} },
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};
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u8 MR13Value;
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u8 MR14Value[CHANNEL_MAX][RANK_MAX][FSP_MAX] = {
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{{0x5d, 0x10}, {0x5d, 0x10} }, {{0x5d, 0x10}, {0x5d, 0x10} },
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};
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u8 MR22Value[FSP_MAX] = {0x38, 0x34};
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MR01Value[FSP_0] &= 0x8f;
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MR01Value[FSP_1] &= 0x8f;
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MR01Value[FSP_0] = 0x6;
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MR01Value[FSP_1] = 0x6;
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if (freq_group == LP4X_DDR1600) {
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MR02Value[0] = 0x12;
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@ -838,6 +838,8 @@ static void dramc_mode_reg_init(u8 freq_group)
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(2 << 0) | (MR02Value[operate_fsp] << 16));
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}
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mr->MR13Value = MR13Value;
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clrsetbits_le32(&ch[0].ao.mrs, 0x3 << 24, RANK_0 << 24);
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clrsetbits_le32(&ch[1].ao.mrs, 0x3 << 24, RANK_0 << 24);
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dramc_set_broadcast(broadcast_bak);
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@ -1730,13 +1732,13 @@ static void ddr_update_ac_timing(u8 freq_group)
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}
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void dramc_init(const struct sdram_params *params, u8 freq_group,
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const struct dram_impedance *impedance)
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struct dram_shared_data *shared)
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{
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dramc_setting(params, freq_group, impedance);
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dramc_setting(params, freq_group, &shared->impedance);
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dramc_duty_calibration(params, freq_group);
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dvfs_settings(freq_group);
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dramc_mode_reg_init(freq_group);
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dramc_mode_reg_init(freq_group, &shared->mr);
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ddr_update_ac_timing(freq_group);
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}
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@ -84,9 +84,6 @@ struct per_byte_dly {
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u16 final_dly;
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};
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extern u8 MR01Value[FSP_MAX];
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extern u8 MR13Value;
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static void dramc_auto_refresh_switch(u8 chn, bool option)
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{
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SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, option ? 0 : 1);
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@ -433,24 +430,24 @@ void dramc_apply_config_before_calibration(u8 freq_group)
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}
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}
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static void dramc_set_mr13_vrcg_to_Normal(u8 chn)
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static void dramc_set_mr13_vrcg_to_Normal(u8 chn, const struct mr_value *mr)
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{
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MR13Value &= ~(0x1 << 3);
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for (u8 rank = 0; rank < RANK_MAX; rank++)
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dramc_mode_reg_write_by_rank(chn, rank, 13, MR13Value);
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dramc_mode_reg_write_by_rank(chn, rank, 13,
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mr->MR13Value & ~(0x1 << 3));
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for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
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clrbits_le32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19);
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}
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void dramc_apply_config_after_calibration(void)
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void dramc_apply_config_after_calibration(const struct mr_value *mr)
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{
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for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
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write32(&ch[chn].phy.misc_cg_ctrl4, 0x11400000);
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clrbits_le32(&ch[chn].ao.refctrl1, 0x1 << 7);
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clrbits_le32(&ch[chn].ao.shuctrl, 0x1 << 2);
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clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 6);
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dramc_set_mr13_vrcg_to_Normal(chn);
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dramc_set_mr13_vrcg_to_Normal(chn, mr);
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clrbits_le32(&ch[chn].phy.b[0].dq[6], 0x3);
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clrbits_le32(&ch[chn].phy.b[1].dq[6], 0x3);
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@ -936,7 +933,8 @@ static void dramc_rx_dqs_gating_cal_partial(u8 chn, u8 rank,
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}
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static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group,
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const struct sdram_params *params, const bool fast_calib)
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const struct sdram_params *params, const bool fast_calib,
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const struct mr_value *mr)
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{
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u8 dqs, fsp, freqDiv = 4;
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u8 pass_begin[DQS_NUMBER] = {0}, pass_count[DQS_NUMBER] = {0},
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@ -966,8 +964,7 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group,
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fsp = get_freq_fsq(freq_group);
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dramc_rx_dqs_isi_pulse_cg_switch(chn, false);
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MR01Value[fsp] |= 0x80;
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dramc_mode_reg_write_by_rank(chn, rank, 0x1, MR01Value[fsp]);
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dramc_mode_reg_write_by_rank(chn, rank, 0x1, mr->MR01Value[fsp] | 0x80);
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dramc_rx_dqs_gating_cal_pre(chn, rank);
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u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd);
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@ -1048,8 +1045,7 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group,
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for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
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write32(regs_bak[i].addr, regs_bak[i].value);
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MR01Value[fsp] &= 0x7f;
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dramc_mode_reg_write_by_rank(chn, rank, 0x1, MR01Value[fsp]);
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dramc_mode_reg_write_by_rank(chn, rank, 0x1, mr->MR01Value[fsp]);
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dramc_write_dqs_gating_result(chn, rank, best_coarse_tune2t,
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best_coarse_tune0p5t, best_coarse_tune2t_p1, best_coarse_tune0p5t_p1);
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@ -2099,7 +2095,8 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group)
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(0xff << 8) | (0x9 << 2) | ROEN);
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}
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int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group)
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int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group,
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const struct mr_value *mr)
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{
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bool fast_calib;
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switch (pams->source) {
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@ -2126,7 +2123,7 @@ int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group)
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dramc_auto_refresh_switch(chn, true);
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dramc_rx_dqs_gating_cal(chn, rk, freq_group, pams,
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fast_calib);
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fast_calib, mr);
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dramc_window_perbit_cal(chn, rk, freq_group,
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RX_WIN_RD_DQC, pams, fast_calib);
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dramc_window_perbit_cal(chn, rk, freq_group,
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@ -351,14 +351,14 @@ static void spm_pinmux_setting(void)
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static void dfs_init_for_calibration(const struct sdram_params *params,
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u8 freq_group,
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struct dram_impedance *impedance)
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struct dram_shared_data *shared)
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{
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dramc_init(params, freq_group, impedance);
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dramc_init(params, freq_group, shared);
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dramc_apply_config_before_calibration(freq_group);
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}
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static void init_dram(const struct sdram_params *params, u8 freq_group,
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struct dram_impedance *impedance)
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struct dram_shared_data *shared)
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{
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global_option_init(params);
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emi_init(params);
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@ -367,10 +367,10 @@ static void init_dram(const struct sdram_params *params, u8 freq_group,
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dramc_init_pre_settings();
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spm_pinmux_setting();
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dramc_sw_impedance_cal(params, ODT_OFF, impedance);
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dramc_sw_impedance_cal(params, ODT_ON, impedance);
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dramc_sw_impedance_cal(params, ODT_OFF, &shared->impedance);
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dramc_sw_impedance_cal(params, ODT_ON, &shared->impedance);
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dramc_init(params, freq_group, impedance);
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dramc_init(params, freq_group, shared);
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dramc_apply_config_before_calibration(freq_group);
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emi_init2(params);
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}
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@ -485,7 +485,7 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle)
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}
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static int run_calib(const struct dramc_param *dparam,
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struct dram_impedance *impedance,
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struct dram_shared_data *shared,
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const int shuffle, bool *first_run)
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{
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const u8 *freq_tbl;
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@ -504,13 +504,13 @@ static int run_calib(const struct dramc_param *dparam,
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frequency_table[freq_group], *first_run);
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if (*first_run)
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init_dram(params, freq_group, impedance);
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init_dram(params, freq_group, shared);
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else
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dfs_init_for_calibration(params, freq_group, impedance);
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dfs_init_for_calibration(params, freq_group, shared);
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*first_run = false;
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dramc_dbg("Start K (current clock: %u\n", params->frequency);
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if (dramc_calibrate_all_channels(params, freq_group) != 0)
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if (dramc_calibrate_all_channels(params, freq_group, &shared->mr) != 0)
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return -1;
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dramc_ac_timing_optimize(freq_group);
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dramc_dbg("K finished (current clock: %u\n", params->frequency);
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@ -519,30 +519,30 @@ static int run_calib(const struct dramc_param *dparam,
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return 0;
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}
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static void after_calib(void)
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static void after_calib(const struct mr_value *mr)
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{
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dramc_apply_config_after_calibration();
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dramc_apply_config_after_calibration(mr);
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dramc_runtime_config();
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}
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int mt_set_emi(const struct dramc_param *dparam)
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{
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struct dram_impedance impedance;
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struct dram_shared_data shared;
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bool first_run = true;
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set_vdram1_vddq_voltage();
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if (CONFIG(MT8183_DRAM_DVFS)) {
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if (run_calib(dparam, &impedance, DRAM_DFS_SHUFFLE_3,
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if (run_calib(dparam, &shared, DRAM_DFS_SHUFFLE_3,
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&first_run) != 0)
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return -1;
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if (run_calib(dparam, &impedance, DRAM_DFS_SHUFFLE_2,
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if (run_calib(dparam, &shared, DRAM_DFS_SHUFFLE_2,
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&first_run) != 0)
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return -1;
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}
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if (run_calib(dparam, &impedance, DRAM_DFS_SHUFFLE_1, &first_run) != 0)
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if (run_calib(dparam, &shared, DRAM_DFS_SHUFFLE_1, &first_run) != 0)
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return -1;
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after_calib();
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after_calib(&shared.mr);
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return 0;
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}
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@ -59,4 +59,10 @@ enum {
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CBT_BYTE_MODE1
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};
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enum {
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FSP_0 = 0,
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FSP_1,
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FSP_MAX
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};
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#endif /* _DRAMC_COMMON_MT8183_H_ */
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@ -44,12 +44,6 @@ enum dram_te_op {
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TE_OP_READ_CHECK
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};
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enum {
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FSP_0 = 0,
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FSP_1,
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FSP_MAX
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};
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enum {
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PASS_RANGE_NA = 0x7fff
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};
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@ -107,15 +101,15 @@ void dramc_set_broadcast(u32 onoff);
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u32 dramc_get_broadcast(void);
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u8 get_freq_fsq(u8 freq_group);
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void dramc_init(const struct sdram_params *params, u8 freq_group,
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const struct dram_impedance *impedance);
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struct dram_shared_data *shared);
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void dramc_sw_impedance_save_reg(u8 freq_group,
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const struct dram_impedance *impedance);
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void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term_option,
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struct dram_impedance *impedance);
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void dramc_apply_config_before_calibration(u8 freq_group);
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void dramc_apply_config_after_calibration(void);
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void dramc_apply_config_after_calibration(const struct mr_value *mr);
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int dramc_calibrate_all_channels(const struct sdram_params *pams,
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u8 freq_group);
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u8 freq_group, const struct mr_value *mr);
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void dramc_hw_gating_onoff(u8 chn, bool onoff);
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void dramc_enable_phy_dcm(bool bEn);
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void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value);
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@ -86,6 +86,16 @@ struct dram_impedance {
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u32 data[ODT_MAX][4];
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};
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struct mr_value {
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u8 MR01Value[FSP_MAX];
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u8 MR13Value;
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};
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struct dram_shared_data {
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struct dram_impedance impedance;
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struct mr_value mr;
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};
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extern const u8 phy_mapping[CHANNEL_MAX][16];
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int complex_mem_test(u8 *start, unsigned int len);
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