Docs/releases: Update 4.22 release notes
These should be the final release notes prior to tagging coreboot Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id723f8e1fc92ef1a36e877f48e594eef59b0ba8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79077 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Martin Roth
Martin L Roth
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Upcoming release - coreboot 4.22
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========================================================================
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The 4.22 release is planned for mid-November, 2023
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The next release is planned for mid-February, 2024
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Update this document with changes that should be in the release notes.
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These notes cover the latest updates and improvements to coreboot over
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the past three months. A big thank you to the returning contributors as
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well as the 14 individuals who committed code for the first time. We
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greatly appreciate everyone's dedication and expertise. As with past
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releases, this one reflects a commitment to open source innovation,
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security enhancements, and expanding hardware support.
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* Please use Markdown.
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* See the past few release notes for the general format.
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* The chip and board additions and removals will be updated right
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before the release, so those do not need to be added.
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* Note that all changes before the release are done are marked upcoming.
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A final version of the notes are done after the release.
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### Significant or interesting changes
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### coreboot version naming update
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* Add changes that need a full description here
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This release is the last release to use the incrementing 4.xx release
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name scheme. For future releases, coreboot is switching to a
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Year.Month.Sub-version naming scheme. As such, the next release,
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scheduled for February of 2024 will be numbered 24.02, with the
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sub-version of 00 implied. If we need to do a fix or future release of
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the 24.02 release, we’ll append the values .01, .02 and so on to the
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initial release value.
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* This section should have full descriptions and can or should have
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a link to the referenced commits.
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### coreboot default branch update
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Immediately after the 4.21 release, the coreboot project changed the
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default git branch from ‘master’ to ‘main’. For the first couple of
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months after the change, The master branch was synced with the main
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branch several times a day, allowing people time to update any scripts.
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As of 2023-11-01, the sync rate has slowed to once a week. This will
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continue until the next release, at which time the master branch will
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be removed.
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Significant or interesting changes
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----------------------------------
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### x86: support .data section for pre-memory stages
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x86 pre-memory stages did not support the `.data` section and as a
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result developers were required to include runtime initialization code
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instead of relying on C global variable definition.
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instead of relying on C global variable definitions.
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Other platforms do not have that limitation. Hence, resolving it helps
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to align code and reduce compilation based restriction (cf. the use of
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to align code and reduce compilation-based restrictions (cf. the use of
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`ENV_HAS_DATA_SECTION` compilation flag in various places of coreboot
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code).
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@ -37,92 +55,284 @@ There were three types of binary to consider:
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3. pre-memory stages loaded in and executed from Cache-As-RAM
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(cf. `CONFIG_NO_XIP_EARLY_STAGES`).
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eXecute-In-Place pre-memory stages (#1) relies on a new ELF segment as
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eXecute-In-Place pre-memory stages (#1) rely on a new ELF segment as
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the code segment Virtual Memory Address and Load Memory Address are
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identical but the data needs to be linked in cache-As-RAM (VMA) but to
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be stored right after the code (LMA).
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identical but the data needs to be linked in cache-As-RAM (VMA) to be
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stored right after the code (LMA).
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`bootblock` (#2) also uses this new segment to store the data right
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after the code and it loads it to Cache-As-RAM at runtime. However,
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the code involved is different.
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after the code and it loads it to Cache-As-RAM at runtime. However, the
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code involved is different.
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Not eXecute-In-Place pre-memory stages (#3) did not really need any
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special work other than enabling a .data section as the code and data
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VMA / LMA translation vector is the same.
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Not eXecute-In-Place pre-memory stages (#3) did not need any special
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work other than enabling a .data section as the code and data VMA / LMA
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translation vector is the same.
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Related important commits:
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- c9cae530e5 ("cbfstool: Make add-stage support multiple ignore sections")
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- 79f2e1fc8b ("cbfstool: Make add-stage support multiple loadable segments")
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- b7832de026 ("x86: Add .data section support for pre-memory stages")
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- c9cae530e5ac54c5b3639d0d555966ca5cad65ff ("cbfstool: Make add-stage
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support multiple ignore sections")
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- 79f2e1fc8b6192e96f99c05f71baeb77d4633d40 ("cbfstool: Make add-stage
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support multiple loadable segments")
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- b7832de0260b042c25bf8f53abcb32e20a29ae9c ("x86: Add .data section
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support for pre-memory stages")
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### x86: Support CBFS cache for pre-memory stages and ramstage
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The CBFS cache scratchpad offers a generic way to decompress CBFS
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files through the cbfs_map() function without having to reserve a
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per-file specific memory region.
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The CBFS cache scratchpad offers a generic way to decompress CBFS files
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through the cbfs_map() function without having to reserve a per-file
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specific memory region.
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CBFS cache x86 support has been added to pre-memory stages and
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ramstage.
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1. **pre-memory stages**: The new `PRERAM_CBFS_CACHE_SIZE` Kconfig can
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be used to set the pre-memory stages CBFS cache size. A cache size
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of zero disables the CBFS cache feature for all pre-memory
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stages. The default value is 16 KiB which seems a reasonable
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minimal value enough to satisfy basic needs such as the
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decompression of a small configuration file. This setting can be
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adjusted depending on the platform needs and capabilities.
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of zero disables the CBFS cache feature for all pre-memory stages.
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The default value is 16 KiB which seems a reasonable minimal value
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enough to satisfy basic needs such as the decompression of a small
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configuration file. This setting can be adjusted depending on the
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platform's needs and capabilities.
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Note that we have set this size to zero for all the platforms
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without enough space in Cache-As-RAM to accommodate the default
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size.
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2. **ramstage**: The new `RAMSTAGE_CBFS_CACHE_SIZE` Kconfig can be
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used to set the ramstage CBFS cache size. A cache size of zero
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disables the CBFS cache feature for ramstage. Similarly to
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pre-memory stages support, the default size is 16 KiB.
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2. **ramstage**: The new `RAMSTAGE_CBFS_CACHE_SIZE` Kconfig can be used
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to set the ramstage CBFS cache size. A cache size of zero disables
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the CBFS cache feature for ramstage. Similarly to pre-memory stages
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support, the default size is 16 KiB.
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As we want to support S3 suspend/resume use-case, the CBFS cache
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As we want to support the S3 suspend/resume use case, the CBFS cache
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memory cannot be released to the operating system and therefore
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cannot be an unreserved memory region. The ramstage CBFS cache
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scratchpad is defined as a simple C static buffer as it allows us
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to keep the simple and robust design of the static initialization
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of the `cbfs_cache` global variable (cf. src/lib/cbfs.c).
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scratchpad is defined as a simple C static buffer as it allows us to
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keep the simple and robust design of the static initialization of
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the `cbfs_cache` global variable (cf. src/lib/cbfs.c).
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However, since some AMD SoCs (cf. `SOC_AMD_COMMON_BLOCK_NONCAR`
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Kconfig) already define a `_cbfs_cache` region we also introduced a
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`POSTRAM_CBFS_CACHE_IN_BSS` Kconfig to gate the use of a static
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buffer as the CBFS cache scratchpad.
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### Allow romstage to be combined into the bootblock
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Having a separate romstage is only desirable:
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- with advanced setups like vboot or normal/fallback
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- boot medium is slow at startup (some ARM SOCs)
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- bootblock is limited in size (Intel APL 32K)
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When this is not the case there is no need for the extra complexity
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that romstage brings. Including the romstage sources inside the
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bootblock substantially reduces the total code footprint. Often the
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resulting code is 10-20k smaller.
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This is controlled via a Kconfig option.
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### soc/intel/cmn/gfx: Add API to report presence of external display
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This implements an API to report the presence of an external display on
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Intel silicon. The API uses information from the transcoder and
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framebuffer to determine if an external display is connected.
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For example, if the transcoder is attached to any DDI ports other than
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DDI-A (eDP), and the framebuffer is initialized, then it is likely that
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an external display is present.
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This information can be used by payloads to determine whether or not to
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power on the display, even if eDP is not initialized.
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### device/pci_rom: Set VBIOS checksum when filling VFCT table
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AMD's Windows display drivers validate the checksum of the VBIOS data
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in the VFCT table (which gets modified by the FSP GOP driver), so
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ensure it is set correctly after copying the VBIOS into the table if
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the FSP GOP driver was run. Without the correct checksum, the Windows
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GPU drivers will fail to load with a code 43 error in Device Manager.
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Additional coreboot changes
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---------------------------
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* Move all ‘select’ statements from Kconfig.name files to Kconfig
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* acpigen now generates variable-length PkgLength fields instead of a
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fixed 3-byte size to improve compatibility and to bring it in line
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with IASL
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* Work to allow Windows to run on more Chromebooks
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* General cleanup and reformatting
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* Add initial AMD openSIL implementation
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* Add ACPI table generation for ARM64
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* Stop resetting CMOS during s3 resume even if marked as invalid
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* Comply with ACPI specification by making _STR Unicode strings
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* Fix SMM get_save_state calculation, which was broken when STM was
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enabled
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* SNB+MRC boards: Migrate MRC settings to devicetree
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* Work on chipset devicetrees for all platforms
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Changes to external resources
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-----------------------------
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### Toolchain updates
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* Upgrade GMP from 6.2.1 to 6.3.0
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* Upgrade binutils from 2.40 to 2.41
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* Upgrade MPFR from 4.2.0 to 4.2.1
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### Additional coreboot changes
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The following are changes across a number of patches, or changes worth
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noting, but not needing a full description.
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### Git submodule pointers
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* Changes that only need a line or two of description go here.
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### Platform Updates
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* To be filled in immediately before the release by the release team
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### Plans to move platform support to a branch
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* Section to be filled in or removed after discussion
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### Statistics from the 4.21 to the 4.22 release
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* To be filled in immediately before the release by the release team
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* amd_blobs: Update from commit id 6a1e1457af to e4519efca7 (16
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commits)
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* arm-trusted-firmware: Update from commit id 37366af8d4 to 88b2d81345
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(214 commits)
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* fsp: Update from commit id 3beceb01f9 to 481ea7cf0b (15 commits)
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* intel-microcode: Update from commit id 6f36ebde45 to 6788bb07eb (1
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commit)
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* vboot: Update from commit id 0c11187c75 to 24cb127a5e (24 commits)
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* genoa_poc/opensil: New submodule updated to 0411c75e17 (41 commits)
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### Significant Known and Open Issues
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### External payloads
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* To be filled in immediately before the release by the release team
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* U-Boot: Use github mirror and the latest version
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* edk2: Update default branch for MrChromebox repo to 2023-09
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Platform Updates
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----------------
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### Added 17 mainboards
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* AMD Onyx
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* Google: Anraggar
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* Google: Brox
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* Google: Chinchou
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* Google: Ciri
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* Google: Deku
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* Google: Deku4ES
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* Google: Dexi
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* Google: Dochi
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* Google: Nokris
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* Google: Quandiso
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* Google: Rex4ES EC ISH
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* Intel: Meteorlake-P RVP with Chrome EC for non-Prod Silicon
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* Purism Librem 11
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* Purism Librem L1UM v2
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* Siemens FA EHL
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* Supermicro X11SSW-F
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### Added 1 SoC
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* src/soc/amd/genoa
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Statistics from the 4.21 to the 4.22 release
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--------------------------------------------
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* Total Commits: 885
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* Average Commits per day: 10.72
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* Total lines added: 58276
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* Average lines added per commit: 65.85
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* Number of patches adding more than 100 lines: 54
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* Average lines added per small commit: 37.77
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* Total lines removed: 27790
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* Average lines removed per commit: 31.40
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* Total difference between added and removed: 30486
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* Total authors: 135
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* New authors: 14
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Significant Known and Open Issues
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---------------------------------
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Issues from the coreboot bugtracker: https://ticket.coreboot.org/
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### Payload-specific issues
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```eval_rst
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+-----+-----------------------------------------------------------------+
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| # | Subject |
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+=====+=================================================================+
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| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled |
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+-----+-----------------------------------------------------------------+
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| 496 | Missing malloc check in libpayload |
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+-----+-----------------------------------------------------------------+
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| 484 | No USB keyboard support with secondary payloads |
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+-----+-----------------------------------------------------------------+
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| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
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+-----+-----------------------------------------------------------------+
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```
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### Platform-specific issues
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```eval_rst
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+-----+-----------------------------------------------------------------+
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| # | Subject |
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+=====+=================================================================+
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| 509 | SD Card hotplug not working on Apollo Lake |
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+-----+-----------------------------------------------------------------+
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| 507 | Windows GPU driver fails on Google guybrush & skyrim boards |
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+-----+-----------------------------------------------------------------+
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| 506 | APL/GML don't boot OS when CPU microcode included "from tree" |
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+-----+-----------------------------------------------------------------+
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| 505 | Harcuvar CRB - 15 of 16 cores present in the operating system |
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+-----+-----------------------------------------------------------------+
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| 499 | T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled |
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+-----+-----------------------------------------------------------------+
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| 495 | Stoney Chromebooks not booting PSPSecureOS |
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+-----+-----------------------------------------------------------------+
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| 478 | X200 booting Linux takes a long time with TSC |
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+-----+-----------------------------------------------------------------+
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| 474 | X200s crashes after graphic init with 8GB RAM |
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+-----+-----------------------------------------------------------------+
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| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb |
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+-----+-----------------------------------------------------------------+
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| 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit |
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+-----+-----------------------------------------------------------------+
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| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
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+-----+-----------------------------------------------------------------+
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| 448 | Thinkpad T440P ACPI Battery Value Issues |
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+-----+-----------------------------------------------------------------+
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| 446 | Optiplex 9010 No Post |
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+-----+-----------------------------------------------------------------+
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| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz) |
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+-----+-----------------------------------------------------------------+
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| 427 | x200: Two battery charging issues |
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+-----+-----------------------------------------------------------------+
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| 412 | x230 reboots on suspend |
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+-----+-----------------------------------------------------------------+
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| 393 | T500 restarts rather than waking up from suspend |
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+-----+-----------------------------------------------------------------+
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| 350 | I225 PCIe device not detected on Harcuvar |
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+-----+-----------------------------------------------------------------+
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```
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Plans for the next release
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--------------------------
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* Finish adding chipset device trees for all SOCs
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* Improve code for options/setup
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* Start reformatting C files with clang-format
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* Add warning/error step for Makefiles at the end
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coreboot Links and Contact Information
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--------------------------------------
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* Main Website: https://www.coreboot.org
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* Downloads: https://coreboot.org/downloads.html
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* Source control: https://review.coreboot.org
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* Documentation: https://doc.coreboot.org
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* Issue tracker: https://ticket.coreboot.org/projects/coreboot
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* Donations: https://coreboot.org/donate.html
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