lenovo/x220: New port
Change-Id: Ic213948e4d31457dda9b9f2d5a4f92cd34d1e57d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6757 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Vladimir Serbinenko
parent
309fc4ce8b
commit
94930e2622
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@ -22,6 +22,11 @@ config BOARD_LENOVO_X201
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help
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Lenovo X201 laptop. Consult wiki for details.
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config BOARD_LENOVO_X220
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bool "ThinkPad X220"
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help
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Lenovo X220 laptop. Consult wiki for details.
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config BOARD_LENOVO_X230
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bool "ThinkPad X230"
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help
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@ -50,6 +55,7 @@ endchoice
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source "src/mainboard/lenovo/x60/Kconfig"
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source "src/mainboard/lenovo/x200/Kconfig"
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source "src/mainboard/lenovo/x201/Kconfig"
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source "src/mainboard/lenovo/x220/Kconfig"
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source "src/mainboard/lenovo/x230/Kconfig"
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source "src/mainboard/lenovo/t520/Kconfig"
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source "src/mainboard/lenovo/t530/Kconfig"
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@ -0,0 +1,86 @@
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if BOARD_LENOVO_X220
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
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select SOUTHBRIDGE_INTEL_C216
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select EC_LENOVO_PMH7
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select EC_LENOVO_H8
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select BOARD_ROMSIZE_KB_8192
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select HAVE_ACPI_RESUME
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select HAVE_SMI_HANDLER
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select EARLY_CBMEM_INIT
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select VGA
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select INTEL_EDID
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
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select SANDYBRIDGE_LVDS
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# Workaround for EC/KBC IRQ1.
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select SERIRQ_CONTINUOUS_MODE
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config HAVE_MRC_CACHE
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bool
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default y
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config HAVE_IFD_BIN
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bool
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default n
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config HAVE_ME_BIN
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bool
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default n
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config MAINBOARD_DIR
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string
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default lenovo/x220
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config MAINBOARD_PART_NUMBER
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string
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default "4299Y48"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config IRQ_SLOT_COUNT
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int
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default 18
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config MAX_CPUS
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int
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default 8
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config USBDEBUG_HCD_INDEX
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int
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default 2
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config DRAM_RESET_GATE_GPIO
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int
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default 10
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config VGA_BIOS_FILE
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string
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default "pci8086,0126.rom"
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config VGA_BIOS_ID
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string
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default "8086,0126"
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x17aa
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x21db
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config MAINBOARD_VENDOR
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string
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default "LENOVO"
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endif # BOARD_LENOVO_X220
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@ -0,0 +1,20 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <ec/lenovo/h8/acpi/ec.asl>
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Scope(\_SB.PCI0.LPCB.EC)
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{
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}
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@ -0,0 +1,13 @@
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Method (_L01, 0, NotSerialized)
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{
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If (\_SB.PCI0.RP04.HPCS)
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{
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Sleep (100)
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Store (0x01, \_SB.PCI0.RP04.HPCS)
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If (\_SB.PCI0.RP04.PDC)
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{
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Store (0x01, \_SB.PCI0.RP04.PDC)
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Notify (\_SB.PCI0.RP04, 0x00)
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}
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}
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}
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@ -0,0 +1,77 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* The APM port can be used for generating software SMIs */
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OperationRegion (APMP, SystemIO, 0xb2, 2)
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Field (APMP, ByteAcc, NoLock, Preserve)
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{
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APMC, 8, // APM command
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APMS, 8 // APM status
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}
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/* Port 80 POST */
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OperationRegion (POST, SystemIO, 0x80, 1)
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Field (POST, ByteAcc, Lock, Preserve)
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{
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DBG0, 8
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}
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/* SMI I/O Trap */
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Method(TRAP, 1, Serialized)
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{
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Store (Arg0, SMIF) // SMI Function
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Store (0, TRP0) // Generate trap
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Return (SMIF) // Return value of SMI handler
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}
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/* The _PIC method is called by the OS to choose between interrupt
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* routing via the i8259 interrupt controller or the APIC.
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*
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* _PIC is called with a parameter of 0 for i8259 configuration and
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* with a parameter of 1 for Local Apic/IOAPIC configuration.
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*/
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Method(_PIC, 1)
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{
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// Remember the OS' IRQ routing choice.
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Store(Arg0, PICM)
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}
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/* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method(_PTS,1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method(_WAK,1)
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{
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/* ME may not be up yet. */
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Store (0, \_TZ.MEB1)
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Store (0, \_TZ.MEB2)
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/* Not implemented. */
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Return(Package(){0,0})
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}
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@ -0,0 +1,64 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* This is board specific information: IRQ routing for Sandybridge */
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// PCI Interrupt Routing
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Method(_PRT)
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{
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If (PICM) {
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Return (Package() {
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI)
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI)
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB
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Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF
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Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD
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// EHCI #1 0:1d.0
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Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD
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// EHCI #2 0:1a.0
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Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF
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// LPC devices 0:1f.0
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Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI)
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Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH
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Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA
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})
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} Else {
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Return (Package() {
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
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Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
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// EHCI #1 0:1d.0
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Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
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// EHCI #2 0:1a.0
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Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
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// LPC device 0:1f.0
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Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
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Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
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})
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}
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}
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@ -0,0 +1 @@
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#include "../../../../drivers/pc80/ps2_controller.asl"
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@ -0,0 +1,253 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <string.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <arch/acpi.h>
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#include <arch/ioapic.h>
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#include <arch/acpigen.h>
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#include <arch/smp/mpspec.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/msr.h>
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extern const unsigned char AmlCode[];
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#if CONFIG_HAVE_ACPI_SLIC
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unsigned long acpi_create_slic(unsigned long current);
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#endif
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/nvs.h>
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#include "thermal.h"
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static void acpi_update_thermal_table(global_nvs_t *gnvs)
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{
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gnvs->tcrt = CRITICAL_TEMPERATURE;
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gnvs->tpsv = PASSIVE_TEMPERATURE;
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}
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static void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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memset((void *)gnvs, 0, sizeof(*gnvs));
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gnvs->apic = 1;
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gnvs->mpen = 1; /* Enable Multi Processing */
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gnvs->pcnt = dev_count_cpu();
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/* Disable USB ports in S3 by default */
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gnvs->s3u0 = 0;
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gnvs->s3u1 = 0;
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/* Disable USB ports in S5 by default */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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/* IGD Displays */
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gnvs->ndid = 3;
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gnvs->did[0] = 0x80000100;
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gnvs->did[1] = 0x80000240;
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gnvs->did[2] = 0x80000410;
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gnvs->did[3] = 0x80000410;
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gnvs->did[4] = 0x00000005;
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// the lid is open by default.
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gnvs->lids = 1;
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acpi_update_thermal_table(gnvs);
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}
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unsigned long acpi_fill_madt(unsigned long current)
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{
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/* Local APICs */
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current = acpi_create_madt_lapics(current);
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/* IOAPIC */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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2, IO_APIC_ADDR, 0);
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/* INT_SRC_OVR */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 0, 2, 0);
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
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return current;
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}
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unsigned long acpi_fill_ssdt_generator(unsigned long current,
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const char *oem_table_id)
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{
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generate_cpu_entries();
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return (unsigned long) (acpigen_get_current());
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}
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unsigned long acpi_fill_slit(unsigned long current)
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{
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// Not implemented
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return current;
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}
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unsigned long acpi_fill_srat(unsigned long current)
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{
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/* No NUMA, no SRAT */
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return current;
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}
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#define ALIGN_CURRENT current = (ALIGN(current, 16))
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unsigned long write_acpi_tables(unsigned long start)
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{
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unsigned long current;
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int i;
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acpi_rsdp_t *rsdp;
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acpi_rsdt_t *rsdt;
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acpi_xsdt_t *xsdt;
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acpi_hpet_t *hpet;
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acpi_madt_t *madt;
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acpi_mcfg_t *mcfg;
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acpi_fadt_t *fadt;
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acpi_facs_t *facs;
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#if CONFIG_HAVE_ACPI_SLIC
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acpi_header_t *slic;
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#endif
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acpi_header_t *ssdt;
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acpi_header_t *dsdt;
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current = start;
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/* Align ACPI tables to 16byte */
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ALIGN_CURRENT;
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printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
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/* We need at least an RSDP and an RSDT Table */
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rsdp = (acpi_rsdp_t *) current;
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current += sizeof(acpi_rsdp_t);
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ALIGN_CURRENT;
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rsdt = (acpi_rsdt_t *) current;
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current += sizeof(acpi_rsdt_t);
|
||||
ALIGN_CURRENT;
|
||||
xsdt = (acpi_xsdt_t *) current;
|
||||
current += sizeof(acpi_xsdt_t);
|
||||
ALIGN_CURRENT;
|
||||
|
||||
/* clear all table memory */
|
||||
memset((void *) start, 0, current - start);
|
||||
|
||||
acpi_write_rsdp(rsdp, rsdt, xsdt);
|
||||
acpi_write_rsdt(rsdt);
|
||||
acpi_write_xsdt(xsdt);
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI: * FACS\n");
|
||||
facs = (acpi_facs_t *) current;
|
||||
current += sizeof(acpi_facs_t);
|
||||
ALIGN_CURRENT;
|
||||
acpi_create_facs(facs);
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI: * DSDT\n");
|
||||
dsdt = (acpi_header_t *) current;
|
||||
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
|
||||
current += dsdt->length;
|
||||
memcpy(dsdt, &AmlCode, dsdt->length);
|
||||
|
||||
ALIGN_CURRENT;
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI: * FADT\n");
|
||||
fadt = (acpi_fadt_t *) current;
|
||||
current += sizeof(acpi_fadt_t);
|
||||
ALIGN_CURRENT;
|
||||
|
||||
acpi_create_fadt(fadt, facs, dsdt);
|
||||
acpi_add_table(rsdp, fadt);
|
||||
|
||||
/*
|
||||
* We explicitly add these tables later on:
|
||||
*/
|
||||
printk(BIOS_DEBUG, "ACPI: * HPET\n");
|
||||
|
||||
hpet = (acpi_hpet_t *) current;
|
||||
current += sizeof(acpi_hpet_t);
|
||||
ALIGN_CURRENT;
|
||||
acpi_create_hpet(hpet);
|
||||
acpi_add_table(rsdp, hpet);
|
||||
|
||||
/* If we want to use HPET Timers Linux wants an MADT */
|
||||
printk(BIOS_DEBUG, "ACPI: * MADT\n");
|
||||
|
||||
madt = (acpi_madt_t *) current;
|
||||
acpi_create_madt(madt);
|
||||
current += madt->header.length;
|
||||
ALIGN_CURRENT;
|
||||
acpi_add_table(rsdp, madt);
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI: * MCFG\n");
|
||||
mcfg = (acpi_mcfg_t *) current;
|
||||
acpi_create_mcfg(mcfg);
|
||||
current += mcfg->header.length;
|
||||
ALIGN_CURRENT;
|
||||
acpi_add_table(rsdp, mcfg);
|
||||
|
||||
/* Pack GNVS into the ACPI table area */
|
||||
for (i=0; i < dsdt->length; i++) {
|
||||
if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
|
||||
printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
|
||||
"DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
|
||||
*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
|
||||
acpi_save_gnvs(current);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* And fill it */
|
||||
acpi_create_gnvs((global_nvs_t *)current);
|
||||
|
||||
/* And tell SMI about it */
|
||||
smm_setup_structures((void *)current, NULL, NULL);
|
||||
|
||||
current += sizeof(global_nvs_t);
|
||||
ALIGN_CURRENT;
|
||||
|
||||
/* We patched up the DSDT, so we need to recalculate the checksum */
|
||||
dsdt->checksum = 0;
|
||||
dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
|
||||
dsdt->length);
|
||||
|
||||
#if CONFIG_HAVE_ACPI_SLIC
|
||||
printk(BIOS_DEBUG, "ACPI: * SLIC\n");
|
||||
slic = (acpi_header_t *)current;
|
||||
current += acpi_create_slic(current);
|
||||
ALIGN_CURRENT;
|
||||
acpi_add_table(rsdp, slic);
|
||||
#endif
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI: * SSDT\n");
|
||||
ssdt = (acpi_header_t *)current;
|
||||
acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
|
||||
current += ssdt->length;
|
||||
acpi_add_table(rsdp, ssdt);
|
||||
ALIGN_CURRENT;
|
||||
|
||||
printk(BIOS_DEBUG, "current = %lx\n", current);
|
||||
printk(BIOS_INFO, "ACPI: done.\n");
|
||||
return current;
|
||||
}
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
Category: laptop
|
||||
Board name: X220
|
||||
ROM package: SOIC-8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: n
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
boot_option=Fallback
|
||||
last_boot=Fallback
|
||||
baud_rate=115200
|
||||
debug_level=Spew
|
||||
power_on_after_fail=Enable
|
||||
nmi=Enable
|
||||
volume=0x3
|
||||
first_battery=Primary
|
||||
bluetooth=Enable
|
||||
wwan=Enable
|
||||
wlan=Enable
|
||||
touchpad=Enable
|
||||
sata_mode=AHCI
|
||||
fn_ctrl_swap=Disable
|
||||
sticky_fn=Disable
|
||||
trackpoint=Enable
|
||||
hyper_threading=Enable
|
||||
|
|
@ -0,0 +1,167 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007-2008 coresystems GmbH
|
||||
## Copyright (C) 2014 Vladimir Serbinenko
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register A
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register B
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register C
|
||||
#96 4 r 0 status_c_rsvd
|
||||
#100 1 r 0 uf_flag
|
||||
#101 1 r 0 af_flag
|
||||
#102 1 r 0 pf_flag
|
||||
#103 1 r 0 irqf_flag
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register D
|
||||
#104 7 r 0 status_d_rsvd
|
||||
#111 1 r 0 valid_cmos_ram
|
||||
# -----------------------------------------------------------------
|
||||
# Diagnostic Status Register
|
||||
#112 8 r 0 diag_rsvd1
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
0 120 r 0 reserved_memory
|
||||
#120 264 r 0 unused
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
388 4 r 0 reboot_bits
|
||||
#390 2 r 0 unused?
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# coreboot config options: console
|
||||
392 3 e 5 baud_rate
|
||||
395 4 e 6 debug_level
|
||||
#399 1 r 0 unused
|
||||
|
||||
400 8 h 0 volume
|
||||
|
||||
# coreboot config options: southbridge
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
|
||||
# coreboot config options: EC
|
||||
411 1 e 8 first_battery
|
||||
412 1 e 1 bluetooth
|
||||
413 1 e 1 wwan
|
||||
414 1 e 1 touchpad
|
||||
415 1 e 1 wlan
|
||||
416 1 e 1 trackpoint
|
||||
417 1 e 1 fn_ctrl_swap
|
||||
418 1 e 1 sticky_fn
|
||||
419 1 e 1 power_management_beeps
|
||||
421 1 e 9 sata_mode
|
||||
#422 2 r 1 unused
|
||||
|
||||
# coreboot config options: cpu
|
||||
424 1 e 2 hyper_threading
|
||||
#425 7 r 0 unused
|
||||
|
||||
# coreboot config options: northbridge
|
||||
432 3 e 11 gfx_uma_size
|
||||
#435 549 r 0 unused
|
||||
|
||||
# SandyBridge MRC Scrambler Seed values
|
||||
896 32 r 0 mrc_scrambler_seed
|
||||
928 32 r 0 mrc_scrambler_seed_s3
|
||||
960 16 r 0 mrc_scrambler_seed_chk
|
||||
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 1 Emergency
|
||||
6 2 Alert
|
||||
6 3 Critical
|
||||
6 4 Error
|
||||
6 5 Warning
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
8 0 Secondary
|
||||
8 1 Primary
|
||||
9 0 AHCI
|
||||
9 1 Compatible
|
||||
10 0 Both
|
||||
10 1 Keyboard only
|
||||
10 2 Thinklight only
|
||||
10 3 None
|
||||
11 0 32M
|
||||
11 1 64M
|
||||
11 2 96M
|
||||
11 3 128M
|
||||
11 4 160M
|
||||
11 5 192M
|
||||
11 6 224M
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
checksum 392 415 984
|
||||
|
|
@ -0,0 +1,188 @@
|
|||
chip northbridge/intel/sandybridge
|
||||
|
||||
# Enable DisplayPort Hotplug with 6ms pulse
|
||||
register "gpu_dp_d_hotplug" = "0x06"
|
||||
|
||||
# Enable Panel as LVDS and configure power delays
|
||||
register "gpu_panel_port_select" = "0" # LVDS
|
||||
register "gpu_panel_power_cycle_delay" = "5"
|
||||
register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms
|
||||
register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms
|
||||
register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
|
||||
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
|
||||
register "gpu_use_spread_spectrum_clock" = "1"
|
||||
register "gpu_lvds_dual_channel" = "0"
|
||||
register "gpu_link_frequency_270_mhz" = "1"
|
||||
register "gpu_lvds_num_lanes" = "4"
|
||||
register "gpu_cpu_backlight" = "0x1155"
|
||||
register "gpu_pch_backlight" = "0x06100610"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_rPGA989
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/model_206ax
|
||||
# Magic APIC ID to locate this chip
|
||||
device lapic 0xACAC off end
|
||||
|
||||
# Coordinate with HW_ALL
|
||||
register "pstate_coord_type" = "0xfe"
|
||||
|
||||
register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
|
||||
register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
|
||||
register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
|
||||
|
||||
register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
|
||||
register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
|
||||
register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
|
||||
end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on
|
||||
subsystemid 0x17aa 0x21db
|
||||
end # host bridge
|
||||
device pci 01.0 off end # PCIe Bridge for discrete graphics
|
||||
device pci 02.0 on
|
||||
subsystemid 0x17aa 0x21db
|
||||
end # vga controller
|
||||
|
||||
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
|
||||
register "pirqa_routing" = "0x8b"
|
||||
register "pirqb_routing" = "0x8a"
|
||||
register "pirqc_routing" = "0x8b"
|
||||
register "pirqd_routing" = "0x8b"
|
||||
register "pirqe_routing" = "0x80"
|
||||
register "pirqf_routing" = "0x80"
|
||||
register "pirqg_routing" = "0x80"
|
||||
register "pirqh_routing" = "0x80"
|
||||
|
||||
# GPI routing
|
||||
# 0 No effect (default)
|
||||
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
|
||||
# 2 SCI (if corresponding GPIO_EN bit is also set)
|
||||
register "alt_gp_smi_en" = "0x0000"
|
||||
register "gpi1_routing" = "2"
|
||||
register "gpi8_routing" = "2"
|
||||
|
||||
# Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata)
|
||||
register "sata_port_map" = "0x7"
|
||||
# Set max SATA speed to 6.0 Gb/s
|
||||
register "sata_interface_speed_support" = "0x3"
|
||||
|
||||
register "gen1_dec" = "0x7c1601"
|
||||
register "gen2_dec" = "0x0c15e1"
|
||||
register "gen4_dec" = "0x0c06a1"
|
||||
|
||||
# Enable zero-based linear PCIe root port functions
|
||||
register "pcie_port_coalesce" = "1"
|
||||
|
||||
device pci 16.0 on
|
||||
subsystemid 0x17aa 0x21db
|
||||
end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT
|
||||
device pci 19.0 on
|
||||
subsystemid 0x17aa 0x21ce
|
||||
end # Intel Gigabit Ethernet
|
||||
device pci 1a.0 on
|
||||
subsystemid 0x17aa 0x21db
|
||||
end # USB2 EHCI #2
|
||||
device pci 1b.0 on
|
||||
subsystemid 0x17aa 0x21db
|
||||
end # High Definition Audio
|
||||
device pci 1c.0 on
|
||||
subsystemid 0x17aa 0x21db
|
||||
end # PCIe Port #1
|
||||
device pci 1c.1 on
|
||||
subsystemid 0x17aa 0x21db
|
||||
end # PCIe Port #2 (wlan)
|
||||
device pci 1c.2 on
|
||||
subsystemid 0x17aa 0x21db
|
||||
end # PCIe Port #3
|
||||
device pci 1c.3 on
|
||||
subsystemid 0x17aa 0x21db
|
||||
end # PCIe Port #4
|
||||
device pci 1c.4 on
|
||||
subsystemid 0x17aa 0x21db
|
||||
device pci 00.0 on
|
||||
subsystemid 0x17aa 0x21db
|
||||
end
|
||||
device pci 00.1 on
|
||||
subsystemid 0x17aa 0x21db
|
||||
end
|
||||
end # PCIe Port #5 (SD)
|
||||
device pci 1c.5 off end # PCIe Port #6
|
||||
device pci 1c.6 off end # PCIe Port #7
|
||||
device pci 1c.7 off end # PCIe Port #8
|
||||
device pci 1d.0 on
|
||||
subsystemid 0x17aa 0x21db
|
||||
end # USB2 EHCI #1
|
||||
device pci 1e.0 off end # PCI bridge
|
||||
device pci 1f.0 on #LPC bridge
|
||||
subsystemid 0x17aa 0x21db
|
||||
chip ec/lenovo/pmh7
|
||||
device pnp ff.1 on # dummy
|
||||
end
|
||||
register "backlight_enable" = "0x01"
|
||||
register "dock_event_enable" = "0x01"
|
||||
end
|
||||
|
||||
chip ec/lenovo/h8
|
||||
device pnp ff.2 on # dummy
|
||||
io 0x60 = 0x62
|
||||
io 0x62 = 0x66
|
||||
io 0x64 = 0x1600
|
||||
io 0x66 = 0x1604
|
||||
end
|
||||
|
||||
register "config0" = "0xa6"
|
||||
register "config1" = "0x01"
|
||||
register "config2" = "0xa0"
|
||||
register "config3" = "0x60"
|
||||
|
||||
register "has_keyboard_backlight" = "0"
|
||||
|
||||
register "beepmask0" = "0x00"
|
||||
register "beepmask1" = "0x86"
|
||||
register "has_power_management_beeps" = "1"
|
||||
register "event2_enable" = "0xff"
|
||||
register "event3_enable" = "0xff"
|
||||
register "event4_enable" = "0xd0"
|
||||
register "event5_enable" = "0xfc"
|
||||
register "event6_enable" = "0x00"
|
||||
register "event7_enable" = "0x81"
|
||||
register "event8_enable" = "0x7b"
|
||||
register "event9_enable" = "0xff"
|
||||
register "eventa_enable" = "0x01"
|
||||
register "eventb_enable" = "0xf0"
|
||||
register "eventc_enable" = "0xff"
|
||||
register "eventd_enable" = "0xff"
|
||||
register "evente_enable" = "0x0d"
|
||||
end
|
||||
end # LPC bridge
|
||||
device pci 1f.2 on
|
||||
subsystemid 0x17aa 0x21db
|
||||
end # SATA Controller 1
|
||||
device pci 1f.3 on
|
||||
subsystemid 0x17aa 0x21db
|
||||
# eeprom, 8 virtual devices, same chip
|
||||
chip drivers/i2c/at24rf08c
|
||||
device i2c 54 on end
|
||||
device i2c 55 on end
|
||||
device i2c 56 on end
|
||||
device i2c 57 on end
|
||||
device i2c 5c on end
|
||||
device i2c 5d on end
|
||||
device i2c 5e on end
|
||||
device i2c 5f on end
|
||||
end
|
||||
end # SMBus
|
||||
device pci 1f.5 off end # SATA Controller 2
|
||||
device pci 1f.6 on
|
||||
subsystemid 0x17aa 0x21db
|
||||
end # Thermal
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define THINKPAD_EC_GPE 17
|
||||
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
|
||||
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
|
||||
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
|
||||
#define RP04_IS_EXPRESSCARD 1
|
||||
#define EC_LENOVO_H8_ME_WORKAROUND 1
|
||||
#define HAVE_LCD_SCREEN 1
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
// Some generic macros
|
||||
#include "acpi/platform.asl"
|
||||
|
||||
// global NVS and variables
|
||||
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
|
||||
// General Purpose Events
|
||||
//#include "acpi/gpe.asl"
|
||||
|
||||
#include <cpu/intel/model_206ax/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
}
|
||||
}
|
||||
|
||||
/* Chipset specific sleep states */
|
||||
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
|
||||
}
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
|
||||
0x40) & 0xfffe;
|
||||
|
||||
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature, "FACP", 4);
|
||||
header->length = sizeof(acpi_fadt_t);
|
||||
header->revision = 3;
|
||||
memcpy(header->oem_id, OEM_ID, 6);
|
||||
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
|
||||
memcpy(header->asl_compiler_id, "CORE", 4);
|
||||
header->asl_compiler_revision = 1;
|
||||
|
||||
fadt->firmware_ctrl = (unsigned long) facs;
|
||||
fadt->dsdt = (unsigned long) dsdt;
|
||||
fadt->model = 1;
|
||||
fadt->preferred_pm_profile = PM_MOBILE;
|
||||
|
||||
fadt->sci_int = 0x9;
|
||||
fadt->smi_cmd = APM_CNT;
|
||||
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
|
||||
fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
|
||||
fadt->s4bios_req = 0x0;
|
||||
fadt->pstate_cnt = 0;
|
||||
|
||||
fadt->pm1a_evt_blk = pmbase;
|
||||
fadt->pm1b_evt_blk = 0x0;
|
||||
fadt->pm1a_cnt_blk = pmbase + 0x4;
|
||||
fadt->pm1b_cnt_blk = 0x0;
|
||||
fadt->pm2_cnt_blk = pmbase + 0x50;
|
||||
fadt->pm_tmr_blk = pmbase + 0x8;
|
||||
fadt->gpe0_blk = pmbase + 0x20;
|
||||
fadt->gpe1_blk = 0;
|
||||
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
fadt->pm2_cnt_len = 1;
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->gpe0_blk_len = 16;
|
||||
fadt->gpe1_blk_len = 0;
|
||||
fadt->gpe1_base = 0;
|
||||
fadt->cst_cnt = 0;
|
||||
fadt->p_lvl2_lat = 101; /* c2 not supported */
|
||||
fadt->p_lvl3_lat = 87;
|
||||
fadt->flush_size = 1024;
|
||||
fadt->flush_stride = 16;
|
||||
fadt->duty_offset = 1;
|
||||
fadt->duty_width = 3;
|
||||
fadt->day_alrm = 0xd;
|
||||
fadt->mon_alrm = 0x00;
|
||||
fadt->century = 0x00;
|
||||
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
|
||||
|
||||
fadt->flags = ACPI_FADT_WBINVD |
|
||||
ACPI_FADT_C1_SUPPORTED |
|
||||
ACPI_FADT_SLEEP_BUTTON |
|
||||
ACPI_FADT_RESET_REGISTER |
|
||||
ACPI_FADT_SEALED_CASE |
|
||||
ACPI_FADT_S4_RTC_WAKE |
|
||||
ACPI_FADT_PLATFORM_CLOCK;
|
||||
|
||||
fadt->reset_reg.space_id = 1;
|
||||
fadt->reset_reg.bit_width = 8;
|
||||
fadt->reset_reg.bit_offset = 0;
|
||||
fadt->reset_reg.resv = 0;
|
||||
fadt->reset_reg.addrl = 0xcf9;
|
||||
fadt->reset_reg.addrh = 0;
|
||||
|
||||
fadt->reset_value = 6;
|
||||
fadt->x_firmware_ctl_l = (unsigned long)facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
fadt->x_dsdt_l = (unsigned long)dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
fadt->x_pm1a_evt_blk.space_id = 1;
|
||||
fadt->x_pm1a_evt_blk.bit_width = 32;
|
||||
fadt->x_pm1a_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_evt_blk.resv = 0;
|
||||
fadt->x_pm1a_evt_blk.addrl = pmbase;
|
||||
fadt->x_pm1a_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_evt_blk.space_id = 1;
|
||||
fadt->x_pm1b_evt_blk.bit_width = 0;
|
||||
fadt->x_pm1b_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_evt_blk.resv = 0;
|
||||
fadt->x_pm1b_evt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1a_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1a_cnt_blk.bit_width = 16;
|
||||
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_cnt_blk.resv = 0;
|
||||
fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
|
||||
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1b_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm1b_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_cnt_blk.resv = 0;
|
||||
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm2_cnt_blk.space_id = 1;
|
||||
fadt->x_pm2_cnt_blk.bit_width = 8;
|
||||
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm2_cnt_blk.resv = 0;
|
||||
fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
|
||||
fadt->x_pm2_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm_tmr_blk.space_id = 1;
|
||||
fadt->x_pm_tmr_blk.bit_width = 32;
|
||||
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||
fadt->x_pm_tmr_blk.resv = 0;
|
||||
fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
|
||||
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe0_blk.space_id = 1;
|
||||
fadt->x_gpe0_blk.bit_width = 128;
|
||||
fadt->x_gpe0_blk.bit_offset = 0;
|
||||
fadt->x_gpe0_blk.resv = 0;
|
||||
fadt->x_gpe0_blk.addrl = pmbase + 0x20;
|
||||
fadt->x_gpe0_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe1_blk.space_id = 1;
|
||||
fadt->x_gpe1_blk.bit_width = 0;
|
||||
fadt->x_gpe1_blk.bit_offset = 0;
|
||||
fadt->x_gpe1_blk.resv = 0;
|
||||
fadt->x_gpe1_blk.addrl = 0x0;
|
||||
fadt->x_gpe1_blk.addrh = 0x0;
|
||||
|
||||
header->checksum =
|
||||
acpi_checksum((void *) fadt, header->length);
|
||||
}
|
||||
|
|
@ -0,0 +1,267 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* Vendor Name : Conexant
|
||||
* Vendor ID : 0x14f1506e
|
||||
* Subsystem ID : 0x17aa21db
|
||||
* Revision ID : 0x100002
|
||||
*/
|
||||
|
||||
|
||||
static const u32 mainboard_cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590
|
||||
0x17aa21db, // Subsystem ID
|
||||
0x00000077, // Number of 4 dword sets
|
||||
|
||||
/* Bits 31:28 - Codec Address */
|
||||
/* Bits 27:20 - NID */
|
||||
/* Bits 19:8 - Verb ID */
|
||||
/* Bits 7:0 - Payload */
|
||||
|
||||
/* NID 0x01 - NodeInfo */
|
||||
0x001720DB,
|
||||
0x00172121,
|
||||
0x001722AA,
|
||||
0x00172317,
|
||||
|
||||
0x01971C40,
|
||||
0x01971D10,
|
||||
0x01971E21,
|
||||
0x01971F04,
|
||||
|
||||
0x01A71C50,
|
||||
0x01A71D90,
|
||||
0x01A71EA1,
|
||||
0x01A71F61,
|
||||
|
||||
0x01B71C60,
|
||||
0x01B71D10,
|
||||
0x01B71EA1,
|
||||
0x01B71F04,
|
||||
|
||||
0x01C71C1F,
|
||||
0x01C71D40,
|
||||
0x01C71E21,
|
||||
0x01C71F61,
|
||||
|
||||
0x01D71CF0,
|
||||
0x01D71D01,
|
||||
0x01D71EF0,
|
||||
0x01D71F40,
|
||||
|
||||
0x01E71CF0,
|
||||
0x01E71D01,
|
||||
0x01E71EF0,
|
||||
0x01E71F40,
|
||||
|
||||
0x01F71C10,
|
||||
0x01F71D01,
|
||||
0x01F71E17,
|
||||
0x01F71F90,
|
||||
|
||||
0x02071CF0,
|
||||
0x02071D01,
|
||||
0x02071EF0,
|
||||
0x02071F40,
|
||||
|
||||
0x02271CF0,
|
||||
0x02271D01,
|
||||
0x02271EF0,
|
||||
0x02271F40,
|
||||
|
||||
0x02371C70,
|
||||
0x02371D01,
|
||||
0x02371EA6,
|
||||
0x02371F90,
|
||||
|
||||
/*
|
||||
* Hardware EQ Parameters
|
||||
* Sample Rate 88200
|
||||
*/
|
||||
0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F,
|
||||
0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80,
|
||||
0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981,
|
||||
0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80,
|
||||
0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F,
|
||||
0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80,
|
||||
0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E,
|
||||
0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80,
|
||||
0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1,
|
||||
0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80,
|
||||
0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E,
|
||||
0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80,
|
||||
0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983,
|
||||
0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80,
|
||||
0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D,
|
||||
0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80,
|
||||
0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C,
|
||||
0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80,
|
||||
0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3,
|
||||
0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80,
|
||||
0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F,
|
||||
0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80,
|
||||
0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982,
|
||||
0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80,
|
||||
0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E,
|
||||
0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80,
|
||||
0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D,
|
||||
0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80,
|
||||
0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2,
|
||||
0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80,
|
||||
0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F,
|
||||
0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80,
|
||||
0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E,
|
||||
0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80,
|
||||
0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937,
|
||||
0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80,
|
||||
0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971,
|
||||
0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80,
|
||||
0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9,
|
||||
0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80,
|
||||
0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942,
|
||||
0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80,
|
||||
0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C,
|
||||
0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80,
|
||||
0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934,
|
||||
0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80,
|
||||
0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963,
|
||||
0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80,
|
||||
0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9,
|
||||
0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80,
|
||||
0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940,
|
||||
0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80,
|
||||
|
||||
/*
|
||||
* Hardware EQ Parameters
|
||||
* Sample Rate 96000
|
||||
*/
|
||||
0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F,
|
||||
0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80,
|
||||
0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981,
|
||||
0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80,
|
||||
0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F,
|
||||
0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80,
|
||||
0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E,
|
||||
0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80,
|
||||
0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1,
|
||||
0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80,
|
||||
0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E,
|
||||
0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80,
|
||||
0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983,
|
||||
0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80,
|
||||
0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D,
|
||||
0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80,
|
||||
0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C,
|
||||
0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80,
|
||||
0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3,
|
||||
0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80,
|
||||
0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F,
|
||||
0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80,
|
||||
0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982,
|
||||
0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80,
|
||||
0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E,
|
||||
0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80,
|
||||
0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D,
|
||||
0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80,
|
||||
0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1,
|
||||
0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80,
|
||||
0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F,
|
||||
0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80,
|
||||
0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D,
|
||||
0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80,
|
||||
0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938,
|
||||
0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80,
|
||||
0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972,
|
||||
0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80,
|
||||
0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8,
|
||||
0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80,
|
||||
0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941,
|
||||
0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80,
|
||||
0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999,
|
||||
0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80,
|
||||
0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934,
|
||||
0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80,
|
||||
0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966,
|
||||
0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80,
|
||||
0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9,
|
||||
0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80,
|
||||
0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940,
|
||||
0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80,
|
||||
|
||||
/* SAFEDSP Parameters */
|
||||
0x022782C1, 0x02277127, 0x02277227, 0x02278801,
|
||||
0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14,
|
||||
0x02278B0F, 0x0017B008,
|
||||
|
||||
/* Misc entries */
|
||||
0x00B707C0, /* Enable PortB as Output with HP amp */
|
||||
0x00D70740, /* Enable PortD as Output */
|
||||
0x0017A200, /* Disable ClkEn of PortSenseTst */
|
||||
0x0017C621, /* Slave Port - Port A used as microphone input for
|
||||
combo Jack
|
||||
Master Port - Port B used for Jack Presence Detect
|
||||
Enable Combo Jack Detection */
|
||||
0x0017A208, /* Enable ClkEn of PortSenseTst */
|
||||
0x00170500, /* Set power state to D0 */
|
||||
|
||||
/* --- Next Codec --- */
|
||||
|
||||
/* Vendor Name : Intel
|
||||
* Vendor ID : 0x80862806
|
||||
* Subsystem ID : 0x80860101
|
||||
* Revision ID : 0x100000
|
||||
*/
|
||||
/* coreboot specific header */
|
||||
0x80862805, // Codec Vendor / Device ID: Intel PantherPoint HDMI
|
||||
0x80860101, // Subsystem ID
|
||||
0x00000004, // Number of IDs
|
||||
|
||||
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
|
||||
0x30172001,
|
||||
0x30172101,
|
||||
0x30172286,
|
||||
0x30172380,
|
||||
|
||||
/* Pin Complex (NID 0x05) Digital Out at Int HDMI */
|
||||
0x30571c10,
|
||||
0x30571d00,
|
||||
0x30571e56,
|
||||
0x30571f18,
|
||||
|
||||
/* Pin Complex (NID 0x06) Digital Out at Int HDMI */
|
||||
0x30671c20,
|
||||
0x30671d00,
|
||||
0x30671e56,
|
||||
0x30671f18,
|
||||
|
||||
/* Pin Complex (NID 0x07) Digital Out at Int HDMI */
|
||||
0x30771c30,
|
||||
0x30771d00,
|
||||
0x30771e56,
|
||||
0x30771f18
|
||||
};
|
||||
|
||||
static const u32 mainboard_pc_beep_verbs[] = {
|
||||
0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */
|
||||
};
|
||||
|
||||
static const u32 mainboard_pc_beep_verbs_size =
|
||||
ARRAY_SIZE(mainboard_pc_beep_verbs);
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2011-2012 Google Inc.
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <string.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <console/console.h>
|
||||
#if CONFIG_VGA_ROM_RUN
|
||||
#include <x86emu/x86emu.h>
|
||||
#endif
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/interrupt.h>
|
||||
#include <boot/coreboot_tables.h>
|
||||
#include "hda_verb.h"
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <smbios.h>
|
||||
#include <device/pci.h>
|
||||
#include <cbfs.h>
|
||||
#include <pc80/keyboard.h>
|
||||
#include <ec/lenovo/h8/h8.h>
|
||||
#include <build.h>
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
void mainboard_suspend_resume(void)
|
||||
{
|
||||
/* Call SMM finalize() handlers before resume */
|
||||
outb(0xcb, 0xb2);
|
||||
}
|
||||
|
||||
#if CONFIG_VGA_ROM_RUN
|
||||
static int int15_handler(void)
|
||||
{
|
||||
int res = 0;
|
||||
|
||||
printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
|
||||
__func__, X86_AX);
|
||||
|
||||
switch (X86_AX) {
|
||||
case 0x5f34:
|
||||
/*
|
||||
* Set Panel Fitting Hook:
|
||||
* bit 2 = Graphics Stretching
|
||||
* bit 1 = Text Stretching
|
||||
* bit 0 = Centering (do not set with bit1 or bit2)
|
||||
* 0 = video bios default
|
||||
*/
|
||||
X86_AX = 0x005f;
|
||||
X86_CL = 0x00; /* Use video bios default */
|
||||
res = 1;
|
||||
break;
|
||||
case 0x5f35:
|
||||
/*
|
||||
* Boot Display Device Hook:
|
||||
* bit 0 = CRT
|
||||
* bit 1 = TV (eDP)
|
||||
* bit 2 = EFP
|
||||
* bit 3 = LFP
|
||||
* bit 4 = CRT2
|
||||
* bit 5 = TV2 (eDP)
|
||||
* bit 6 = EFP2
|
||||
* bit 7 = LFP2
|
||||
*/
|
||||
X86_AX = 0x005f;
|
||||
X86_CX = 0x0000; /* Use video bios default */
|
||||
res = 1;
|
||||
break;
|
||||
case 0x5f51:
|
||||
/*
|
||||
* Hook to select active LFP configuration:
|
||||
* 00h = No LVDS, VBIOS does not enable LVDS
|
||||
* 01h = Int-LVDS, LFP driven by integrated LVDS decoder
|
||||
* 02h = SVDO-LVDS, LFP driven by SVDO decoder
|
||||
* 03h = eDP, LFP Driven by Int-DisplayPort encoder
|
||||
*/
|
||||
X86_AX = 0x005f;
|
||||
X86_CX = 0x0001; /* Int-LVDS */
|
||||
res = 1;
|
||||
break;
|
||||
case 0x5f70:
|
||||
switch (X86_CH) {
|
||||
case 0:
|
||||
/* Get Mux */
|
||||
X86_AX = 0x005f;
|
||||
X86_CX = 0x0000;
|
||||
res = 1;
|
||||
break;
|
||||
case 1:
|
||||
/* Set Mux */
|
||||
X86_AX = 0x005f;
|
||||
X86_CX = 0x0000;
|
||||
res = 1;
|
||||
break;
|
||||
case 2:
|
||||
/* Get SG/Non-SG mode */
|
||||
X86_AX = 0x005f;
|
||||
X86_CX = 0x0000;
|
||||
res = 1;
|
||||
break;
|
||||
default:
|
||||
/* Interrupt was not handled */
|
||||
printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
|
||||
X86_CH);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
|
||||
break;
|
||||
}
|
||||
return res;
|
||||
}
|
||||
#endif
|
||||
|
||||
const char *smbios_mainboard_bios_version(void)
|
||||
{
|
||||
/* Satisfy thinkpad_acpi. */
|
||||
if (strlen(CONFIG_LOCALVERSION))
|
||||
return "CBET4000 " CONFIG_LOCALVERSION;
|
||||
else
|
||||
return "CBET4000 " COREBOOT_VERSION;
|
||||
}
|
||||
|
||||
const char *smbios_mainboard_version(void)
|
||||
{
|
||||
return "ThinkPad X220";
|
||||
}
|
||||
|
||||
/* Audio Setup */
|
||||
|
||||
static void verb_setup(void)
|
||||
{
|
||||
cim_verb_data = mainboard_cim_verb_data;
|
||||
cim_verb_data_size = sizeof(mainboard_cim_verb_data);
|
||||
pc_beep_verbs = mainboard_pc_beep_verbs;
|
||||
pc_beep_verbs_size = mainboard_pc_beep_verbs_size;
|
||||
|
||||
}
|
||||
|
||||
static void mainboard_init(device_t dev)
|
||||
{
|
||||
RCBA32(0x38c8) = 0x00002005;
|
||||
RCBA32(0x38c4) = 0x00802005;
|
||||
RCBA32(0x38c0) = 0x00000007;
|
||||
|
||||
/* This sneaked in here, because X201 SuperIO chip isn't really
|
||||
connected to anything and hence we don't init it.
|
||||
*/
|
||||
pc_keyboard_init();
|
||||
|
||||
/* Enable expresscard hotplug events. */
|
||||
pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)),
|
||||
0xd8,
|
||||
pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), 0xd8)
|
||||
| (1 << 30));
|
||||
pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 3)),
|
||||
0x42, 0x142);
|
||||
}
|
||||
|
||||
static int mainboard_smbios_data(device_t dev, int *handle, unsigned long *current)
|
||||
{
|
||||
int len;
|
||||
char tpec[] = "IBM ThinkPad Embedded Controller -[ ]-";
|
||||
const char *oem_strings[] = {
|
||||
tpec,
|
||||
};
|
||||
|
||||
h8_build_id_and_function_spec_version(tpec + 35, 17);
|
||||
len = smbios_write_type11(current, (*handle)++, oem_strings, ARRAY_SIZE(oem_strings));
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
// mainboard_enable is executed as first thing after
|
||||
// enumerate_buses().
|
||||
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
dev->ops->init = mainboard_init;
|
||||
dev->ops->get_smbios_data = mainboard_smbios_data;
|
||||
|
||||
#if CONFIG_VGA_ROM_RUN
|
||||
/* Install custom int15 handler for VGA OPROM */
|
||||
mainboard_interrupt_handlers(0x15, &int15_handler);
|
||||
#endif
|
||||
verb_setup();
|
||||
}
|
||||
|
||||
void h8_mainboard_init_dock (void)
|
||||
{
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,265 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2010 coresystems GmbH
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <lib.h>
|
||||
#include <timestamp.h>
|
||||
#include <arch/byteorder.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <cbmem.h>
|
||||
#include <console/console.h>
|
||||
#include "northbridge/intel/sandybridge/sandybridge.h"
|
||||
#include "northbridge/intel/sandybridge/raminit_native.h"
|
||||
#include "southbridge/intel/bd82x6x/pch.h"
|
||||
#include "southbridge/intel/bd82x6x/gpio.h"
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cbfs.h>
|
||||
|
||||
static void pch_enable_lpc(void)
|
||||
{
|
||||
/* X230 EC Decode Range Port60/64, Port62/66 */
|
||||
/* Enable EC, PS/2 Keyboard/Mouse */
|
||||
pci_write_config16(PCH_LPC_DEV, LPC_EN,
|
||||
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
|
||||
COMA_LPC_EN);
|
||||
|
||||
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
|
||||
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
|
||||
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
|
||||
|
||||
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
|
||||
|
||||
pci_write_config32(PCH_LPC_DEV, 0xac,
|
||||
0x80010000);
|
||||
}
|
||||
|
||||
static void rcba_config(void)
|
||||
{
|
||||
/*
|
||||
* GFX INTA -> PIRQA (MSI)
|
||||
* D28IP_P1IP WLAN INTA -> PIRQB
|
||||
* D28IP_P2IP ETH0 INTB -> PIRQF
|
||||
* D28IP_P3IP SDCARD INTC -> PIRQD
|
||||
* D29IP_E1P EHCI1 INTA -> PIRQD
|
||||
* D26IP_E2P EHCI2 INTA -> PIRQF
|
||||
* D31IP_SIP SATA INTA -> PIRQB (MSI)
|
||||
* D31IP_SMIP SMBUS INTB -> PIRQH
|
||||
* D31IP_TTIP THRT INTC -> PIRQA
|
||||
* D27IP_ZIP HDA INTA -> PIRQA (MSI)
|
||||
*
|
||||
* Trackpad interrupt is edge triggered and cannot be shared.
|
||||
* TRACKPAD -> PIRQG
|
||||
|
||||
*/
|
||||
|
||||
/* Device interrupt pin register (board specific) */
|
||||
RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
|
||||
(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
|
||||
RCBA32(D29IP) = (INTA << D29IP_E1P);
|
||||
RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
|
||||
(INTC << D28IP_P3IP);
|
||||
RCBA32(D27IP) = (INTA << D27IP_ZIP);
|
||||
RCBA32(D26IP) = (INTA << D26IP_E2P);
|
||||
RCBA32(D25IP) = (NOINT << D25IP_LIP);
|
||||
RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
|
||||
|
||||
/* Device interrupt route registers */
|
||||
DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
|
||||
DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
|
||||
DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
|
||||
DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
|
||||
DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
|
||||
DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
|
||||
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
|
||||
|
||||
/* Enable IOAPIC (generic) */
|
||||
RCBA16(OIC) = 0x0100;
|
||||
/* PCH BWG says to read back the IOAPIC enable register */
|
||||
(void) RCBA16(OIC);
|
||||
|
||||
/* Disable unused devices (board specific) */
|
||||
RCBA32(FD) = 0x1fe41fe3;
|
||||
RCBA32(BUC) = 0;
|
||||
}
|
||||
|
||||
static void
|
||||
init_usb (void)
|
||||
{
|
||||
const u32 rcba_dump[64] = {
|
||||
/* 3500 */ 0x20000153, 0x20000f57, 0x20000f57, 0x20000f57,
|
||||
/* 3510 */ 0x20000f57, 0x20000f57, 0x20000153, 0x20000153,
|
||||
/* 3520 */ 0x20000f57, 0x20000f57, 0x20000f57, 0x20000f57,
|
||||
/* 3530 */ 0x20000f57, 0x20000f57, 0x00000000, 0x00000000,
|
||||
/* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
/* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
/* 3560 */ 0x020c0001, 0x000024a3, 0x00040002, 0x01000050,
|
||||
/* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
|
||||
/* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
/* 3590 */ 0x00000003, 0x000000c0, 0x00000000, 0x00000000,
|
||||
/* 35a0 */ 0x0fc00201, 0x102d0200, 0x00000000, 0x00000000,
|
||||
/* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
/* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
/* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
/* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
/* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
};
|
||||
int i;
|
||||
/* Activate PMBAR. */
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
|
||||
|
||||
/* Unlock registers. */
|
||||
outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
|
||||
|
||||
for (i = 0; i < 64; i++)
|
||||
write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]);
|
||||
|
||||
pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
|
||||
|
||||
/* Relock registers. */
|
||||
outw (0x0000, DEFAULT_PMBASE | 0x003c);
|
||||
}
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
int s3resume = 0;
|
||||
u32 pm1_cnt;
|
||||
u16 pm1_sts;
|
||||
spd_raw_data spd[4];
|
||||
|
||||
if (MCHBAR16(SSKPD) == 0xCAFE) {
|
||||
outb(0x6, 0xcf9);
|
||||
hlt ();
|
||||
}
|
||||
|
||||
timestamp_init(get_initial_timestamp());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
if (bist == 0)
|
||||
enable_lapic();
|
||||
|
||||
pch_enable_lpc();
|
||||
|
||||
/* Enable GPIOs */
|
||||
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
|
||||
pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
|
||||
|
||||
outl(0x3963a5ff, DEFAULT_GPIOBASE);
|
||||
outl(0x9ebf6aff, DEFAULT_GPIOBASE + 4);
|
||||
outl(0x66ff7ffb, DEFAULT_GPIOBASE + 0xc);
|
||||
outl(0x00000000, DEFAULT_GPIOBASE + 0x18);
|
||||
outl(0x00002043, DEFAULT_GPIOBASE + 0x2c);
|
||||
outl(0x02ff04fe, DEFAULT_GPIOBASE + 0x30);
|
||||
outl(0x1f47fbf5, DEFAULT_GPIOBASE + 0x34);
|
||||
outl(0xbdecff87, DEFAULT_GPIOBASE + 0x38);
|
||||
outl(0x000000f0, DEFAULT_GPIOBASE + 0x40);
|
||||
outl(0x00000ff0, DEFAULT_GPIOBASE + 0x44);
|
||||
outl(0x00000fcf, DEFAULT_GPIOBASE + 0x48);
|
||||
|
||||
init_usb();
|
||||
|
||||
/* Initialize console device(s) */
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
/* Perform some early chipset initialization required
|
||||
* before RAM initialization can work
|
||||
*/
|
||||
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
|
||||
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
|
||||
|
||||
/* Check PM1_STS[15] to see if we are waking from Sx */
|
||||
pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
|
||||
|
||||
/* Read PM1_CNT[12:10] to determine which Sx state */
|
||||
pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
|
||||
|
||||
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
|
||||
if (acpi_s3_resume_allowed()) {
|
||||
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
|
||||
s3resume = 1;
|
||||
/* Clear SLP_TYPE. This will break stage2 but
|
||||
* we care for that when we get there.
|
||||
*/
|
||||
outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
|
||||
}
|
||||
}
|
||||
|
||||
post_code(0x38);
|
||||
/* Enable SPD ROMs and DDR-III DRAM */
|
||||
enable_smbus();
|
||||
|
||||
post_code(0x39);
|
||||
|
||||
post_code(0x3a);
|
||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
||||
|
||||
memset (spd, 0, sizeof (spd));
|
||||
read_spd (&spd[0], 0x50);
|
||||
read_spd (&spd[2], 0x51);
|
||||
|
||||
init_dram_ddr3 (spd, 1, TCK_800MHZ, s3resume);
|
||||
|
||||
timestamp_add_now(TS_AFTER_INITRAM);
|
||||
post_code(0x3c);
|
||||
|
||||
rcba_config();
|
||||
post_code(0x3d);
|
||||
|
||||
MCHBAR16(SSKPD) = 0xCAFE;
|
||||
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
/* If there is no high memory area, we didn't boot before, so
|
||||
* this is not a resume. In that case we just create the cbmem toc.
|
||||
*/
|
||||
|
||||
*(u32 *)CBMEM_BOOT_MODE = 0;
|
||||
*(u32 *)CBMEM_RESUME_BACKUP = 0;
|
||||
|
||||
if (s3resume) {
|
||||
void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
|
||||
if (resume_backup_memory) {
|
||||
*(u32 *)CBMEM_BOOT_MODE = 2;
|
||||
*(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
|
||||
}
|
||||
/* Magic for S3 resume */
|
||||
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
|
||||
} else {
|
||||
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
|
||||
}
|
||||
#endif
|
||||
post_code(0x3f);
|
||||
timestamp_add_now(TS_END_ROMSTAGE);
|
||||
}
|
||||
|
|
@ -0,0 +1,194 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <ec/acpi/ec.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <ec/lenovo/h8/h8.h>
|
||||
#include <delay.h>
|
||||
#include <southbridge/intel/bd82x6x/nvs.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <southbridge/intel/bd82x6x/me.h>
|
||||
#include <northbridge/intel/sandybridge/sandybridge.h>
|
||||
#include <cpu/intel/model_206ax/model_206ax.h>
|
||||
|
||||
/* The southbridge SMI handler checks whether gnvs has a
|
||||
* valid pointer before calling the trap handler
|
||||
*/
|
||||
extern global_nvs_t *gnvs;
|
||||
|
||||
static void mainboard_smm_init(void)
|
||||
{
|
||||
printk(BIOS_DEBUG, "initializing SMI\n");
|
||||
/* Enable 0x1600/0x1600 register pair */
|
||||
ec_set_bit(0x00, 0x05);
|
||||
}
|
||||
|
||||
int mainboard_io_trap_handler(int smif)
|
||||
{
|
||||
static int smm_initialized;
|
||||
|
||||
if (!smm_initialized) {
|
||||
mainboard_smm_init();
|
||||
smm_initialized = 1;
|
||||
}
|
||||
|
||||
switch (smif) {
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* On success, the IO Trap Handler returns 1
|
||||
* On failure, the IO Trap Handler returns a value != 1 */
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void mainboard_smi_brightness_up(void)
|
||||
{
|
||||
u8 value;
|
||||
|
||||
if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
|
||||
pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
|
||||
}
|
||||
|
||||
static void mainboard_smi_brightness_down(void)
|
||||
{
|
||||
u8 value;
|
||||
|
||||
if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
|
||||
pci_write_config8(PCI_DEV(0, 2, 1), 0xf4,
|
||||
(value - 0x10) & 0xf0);
|
||||
}
|
||||
|
||||
static void mainboard_smi_handle_ec_sci(void)
|
||||
{
|
||||
u8 status = inb(EC_SC);
|
||||
u8 event;
|
||||
|
||||
if (!(status & EC_SCI_EVT))
|
||||
return;
|
||||
|
||||
event = ec_query();
|
||||
printk(BIOS_DEBUG, "EC event %02x\n", event);
|
||||
|
||||
switch (event) {
|
||||
case 0x14:
|
||||
/* brightness up */
|
||||
mainboard_smi_brightness_up();
|
||||
break;
|
||||
case 0x15:
|
||||
/* brightness down */
|
||||
mainboard_smi_brightness_down();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void mainboard_smi_gpi(u32 gpi_sts)
|
||||
{
|
||||
if (gpi_sts & (1 << 12))
|
||||
mainboard_smi_handle_ec_sci();
|
||||
}
|
||||
|
||||
static int mainboard_finalized = 0;
|
||||
|
||||
int mainboard_smi_apmc(u8 data)
|
||||
{
|
||||
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
|
||||
u8 tmp;
|
||||
|
||||
printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
|
||||
data);
|
||||
|
||||
if (!pmbase)
|
||||
return 0;
|
||||
|
||||
switch (data) {
|
||||
case APM_CNT_ACPI_ENABLE:
|
||||
/* use 0x1600/0x1604 to prevent races with userspace */
|
||||
ec_set_ports(0x1604, 0x1600);
|
||||
/* route H8SCI to SCI */
|
||||
outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
|
||||
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
|
||||
tmp &= ~0x03;
|
||||
tmp |= 0x02;
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
|
||||
/* discard all events, and enable attention */
|
||||
ec_write(0x80, 0x01);
|
||||
break;
|
||||
case APM_CNT_ACPI_DISABLE:
|
||||
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
|
||||
provide a EC query function */
|
||||
ec_set_ports(0x66, 0x62);
|
||||
/* route H8SCI# to SMI */
|
||||
outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000,
|
||||
pmbase + ALT_GP_SMI_EN);
|
||||
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
|
||||
tmp &= ~0x03;
|
||||
tmp |= 0x01;
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
|
||||
/* discard all events, and enable attention */
|
||||
ec_write(0x80, 0x01);
|
||||
break;
|
||||
case APM_CNT_FINALIZE:
|
||||
printk(BIOS_DEBUG, "APMC: FINALIZE\n");
|
||||
if (mainboard_finalized) {
|
||||
printk(BIOS_DEBUG, "APMC#: Already finalized\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
intel_me_finalize_smm();
|
||||
intel_pch_finalize_smm();
|
||||
intel_sandybridge_finalize_smm();
|
||||
intel_model_206ax_finalize_smm();
|
||||
|
||||
mainboard_finalized = 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mainboard_smi_sleep(u8 slp_typ)
|
||||
{
|
||||
if (slp_typ == 3) {
|
||||
u8 ec_wake = ec_read(0x32);
|
||||
/* If EC wake events are enabled, enable wake on EC WAKE GPE. */
|
||||
if (ec_wake & 0x14) {
|
||||
u32 gpe_rout;
|
||||
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
|
||||
|
||||
/* Enable EC WAKE GPE. */
|
||||
outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN);
|
||||
gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
|
||||
/* Redirect EC WAKE GPE to SCI. */
|
||||
gpe_rout &= ~(3 << 26);
|
||||
gpe_rout |= (2 << 26);
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef X230_THERMAL_H
|
||||
#define X230_THERMAL_H
|
||||
|
||||
/* Temperature which OS will shutdown at */
|
||||
#define CRITICAL_TEMPERATURE 100
|
||||
|
||||
/* Temperature which OS will throttle CPU */
|
||||
#define PASSIVE_TEMPERATURE 90
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue