google/eve: Fixes for devicetree settings
The devicetree settings were incorrect in a few places with respect to the SOC and board design: - IMVP8 VR workaround is for MP2939 and not MP2949 on Eve - IccMax values are incorrect according to KBL-Y EDS - USB2[6] is incorrectly labeled - I2C touch devices do not need probed as they are not optional - PCIe Root Port 5 should be enabled - I2C5 device should not be enabled as it is unused BUG=chrome-os-partner:58666 TEST=manually tested on Eve board Change-Id: I74e092444ead4b40c6d8091b80a691d44e2c6c7d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18200 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
parent
e00365217c
commit
949e34c3ee
1 changed files with 17 additions and 17 deletions
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@ -51,7 +51,6 @@ chip soc/intel/skylake
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register "PmConfigSlpSusMinAssert" = "1" # 500ms
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmTimerDisabled" = "1"
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register "SendVrMbxCmd" = "1" # IMVP8 workaround
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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@ -73,7 +72,7 @@ chip soc/intel/skylake
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#| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 34A | 35A | 35A |
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#| IccMax | 4A | 24A | 24A | 24A | 24A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-------+-------+-------------+-------------+-------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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@ -85,7 +84,7 @@ chip soc/intel/skylake
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(7),
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.icc_max = VR_CFG_AMP(4),
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.voltage_limit = 1520,
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}"
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@ -98,7 +97,7 @@ chip soc/intel/skylake
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.icc_max = VR_CFG_AMP(24),
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.voltage_limit = 1520,
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}"
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@ -111,7 +110,7 @@ chip soc/intel/skylake
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.icc_max = VR_CFG_AMP(24),
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.voltage_limit = 1520,
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}"
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@ -124,7 +123,7 @@ chip soc/intel/skylake
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.icc_max = VR_CFG_AMP(24),
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.voltage_limit = 1520,
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}"
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@ -137,22 +136,25 @@ chip soc/intel/skylake
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.icc_max = VR_CFG_AMP(24),
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.voltage_limit = 1520,
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}"
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# Enable Root port 1.
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# Enable Root port 1 with SRCCLKREQ1#
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register "PcieRpEnable[0]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[0]" = "1"
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# RP 1 uses SRCCLKREQ1#
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register "PcieRpClkReqNumber[0]" = "1"
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# Enable Root port 5 with SRCCLKREQ4#
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register "PcieRpEnable[4]" = "1"
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register "PcieRpClkReqSupport[4]" = "1"
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register "PcieRpClkReqNumber[4]" = "4"
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register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
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register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # H1
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register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
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@ -204,7 +206,6 @@ chip soc/intel/skylake
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register "generic.cid" = "PNP0C50_CID"
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register "generic.desc" = "WCOM_DT_DESC"
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register "generic.irq" = "IRQ_LEVEL_LOW(GPP_E7_IRQ)"
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register "generic.probed" = "1"
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register "hid_desc_reg_offset" = "0x1"
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device i2c 0a on end
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end
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@ -221,7 +222,6 @@ chip soc/intel/skylake
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register "generic.hid" = ""ACPI0C50""
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register "generic.desc" = ""Touchpad""
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register "generic.irq" = "IRQ_LEVEL_LOW(GPP_B3_IRQ)"
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register "generic.probed" = "1"
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register "hid_desc_reg_offset" = "0x0"
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device i2c 49 on end
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end
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@ -234,7 +234,7 @@ chip soc/intel/skylake
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 off end # SATA
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device pci 19.0 on end # UART #2
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device pci 19.1 on end # I2C #5
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device pci 19.1 off end # I2C #5
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device pci 19.2 on end # I2C #4
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device pci 1c.0 on
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chip drivers/intel/wifi
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@ -245,7 +245,7 @@ chip soc/intel/skylake
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.4 on end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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