soc/intel/apollolake: add ability to enable eSPI

Add config option to enable eSPI

TEST=Boot to OS

Change-Id: Ib4634690fe4fdb902fc0bc074a3b66b91921ddd5
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22320
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Bora Guvendik 2017-11-03 12:40:25 -07:00 committed by Subrata Banik
parent c73073c414
commit 94aed8d615
4 changed files with 10 additions and 0 deletions

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@ -2676,6 +2676,7 @@
#define PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM 0x9d56 #define PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM 0x9d56
#define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8 #define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8
#define PCI_DEVICE_ID_INTEL_GLK_LPC 0x31e8 #define PCI_DEVICE_ID_INTEL_GLK_LPC 0x31e8
#define PCI_DEVICE_ID_INTEL_GLK_ESPI 0x3197
#define PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC 0x9d85 #define PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC 0x9d85
#define PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC 0x9d84 #define PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC 0x9d84
#define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83 #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83

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@ -390,4 +390,10 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex hex
default 0x7fff default 0x7fff
config SOC_ESPI
bool
default n
help
Use eSPI bus instead of LPC
endif endif

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@ -45,6 +45,7 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
static const struct pad_config lpc_gpios[] = { static const struct pad_config lpc_gpios[] = {
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) #if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#if !IS_ENABLED(CONFIG_SOC_ESPI)
PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */ PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, UP_20K, DEEP, NF1, HIZCRx1, PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, UP_20K, DEEP, NF1, HIZCRx1,
DISPUPD), /* LPC_CLKOUT0 */ DISPUPD), /* LPC_CLKOUT0 */
@ -62,6 +63,7 @@ static const struct pad_config lpc_gpios[] = {
DISPUPD), /* LPC_CLKRUNB */ DISPUPD), /* LPC_CLKRUNB */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1, PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1,
DISPUPD), /* LPC_FRAMEB*/ DISPUPD), /* LPC_FRAMEB*/
#endif /* !IS_ENABLED(CONFIG_SOC_ESPI) */
#else #else
PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),

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@ -114,6 +114,7 @@ static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM, PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM,
PCI_DEVICE_ID_INTEL_APL_LPC, PCI_DEVICE_ID_INTEL_APL_LPC,
PCI_DEVICE_ID_INTEL_GLK_LPC, PCI_DEVICE_ID_INTEL_GLK_LPC,
PCI_DEVICE_ID_INTEL_GLK_ESPI,
PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC,
PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC,
PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC,