soc/intel/apollolake: add ability to enable eSPI
Add config option to enable eSPI TEST=Boot to OS Change-Id: Ib4634690fe4fdb902fc0bc074a3b66b91921ddd5 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22320 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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@ -2676,6 +2676,7 @@
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#define PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM 0x9d56
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#define PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM 0x9d56
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#define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8
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#define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8
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#define PCI_DEVICE_ID_INTEL_GLK_LPC 0x31e8
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#define PCI_DEVICE_ID_INTEL_GLK_LPC 0x31e8
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#define PCI_DEVICE_ID_INTEL_GLK_ESPI 0x3197
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#define PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC 0x9d85
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#define PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC 0x9d85
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#define PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC 0x9d84
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#define PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC 0x9d84
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#define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83
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#define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83
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@ -390,4 +390,10 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
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hex
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hex
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default 0x7fff
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default 0x7fff
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config SOC_ESPI
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bool
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default n
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help
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Use eSPI bus instead of LPC
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endif
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endif
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@ -45,6 +45,7 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
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static const struct pad_config lpc_gpios[] = {
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static const struct pad_config lpc_gpios[] = {
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#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
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#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
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#if !IS_ENABLED(CONFIG_SOC_ESPI)
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PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */
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PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, UP_20K, DEEP, NF1, HIZCRx1,
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, UP_20K, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_CLKOUT0 */
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DISPUPD), /* LPC_CLKOUT0 */
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@ -62,6 +63,7 @@ static const struct pad_config lpc_gpios[] = {
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DISPUPD), /* LPC_CLKRUNB */
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DISPUPD), /* LPC_CLKRUNB */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1,
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_FRAMEB*/
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DISPUPD), /* LPC_FRAMEB*/
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#endif /* !IS_ENABLED(CONFIG_SOC_ESPI) */
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#else
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#else
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PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),
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@ -114,6 +114,7 @@ static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM,
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PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM,
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PCI_DEVICE_ID_INTEL_APL_LPC,
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PCI_DEVICE_ID_INTEL_APL_LPC,
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PCI_DEVICE_ID_INTEL_GLK_LPC,
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PCI_DEVICE_ID_INTEL_GLK_LPC,
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PCI_DEVICE_ID_INTEL_GLK_ESPI,
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PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC,
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PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC,
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PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC,
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PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC,
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PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC,
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PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC,
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