FSP 1.1: Move common FSP code

Move the FSP common code from the src/soc/intel/common directory into
the src/drivers/intel/fsp1_1 directory.  Rename the Kconfig values
associated with this common code.

BRANCH=none
BUG=None
TEST=Build and run on kunimitsu

Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440
Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306350
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12156
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>

src/drivers/intel/fsp1_1/Kconfig

@@ -116,6 +116,22 @@ config DISPLAY_UPD_DATA
 	  Display the user specified product data prior to memory
 	  initialization.
 
+config FSP_RAM_INIT
+	bool
+	default n
+
+config FSP_ROMSTAGE
+	bool
+	default n
+
+config FSP_STACK
+	bool
+	default n
+
+config FSP_STAGE_CACHE
+	bool
+	default n
+
 config FSP_USES_UPD
 	bool
 	default n
@@ -127,6 +143,11 @@ config GOP_SUPPORT
 	bool "Enable GOP support"
 	default y
 
+config ROMSTAGE_RAM_STACK_SIZE
+	hex "Size of the romstage RAM stack in bytes"
+	default 0x5000
+	depends on FSP_STACK
+
 config USE_GENERIC_FSP_CAR_INC
 	bool
 	default n

src/drivers/intel/fsp1_1/Makefile.inc

@@ -25,12 +25,19 @@ verstage-y += verstage.c
 romstage-y += car.c
 romstage-y += fsp_util.c
 romstage-y += hob.c
+romstage-$(CONFIG_FSP_RAM_INIT) += raminit.c
+romstage-$(CONFIG_FSP_ROMSTAGE) += romstage.c
 romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
+romstage-$(CONFIG_FSP_STACK) += stack.c
+romstage-$(CONFIG_FSP_STAGE_CACHE) += stage_cache.c
 
 ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c
 ramstage-y += fsp_relocate.c
 ramstage-y += fsp_util.c
 ramstage-y += hob.c
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_FSP_STAGE_CACHE) += stage_cache.c
+ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c
 
 CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
 # Where FspUpdVpd.h can be picked up from.

src/drivers/intel/fsp1_1/fsp_util.c

@@ -248,3 +248,49 @@ void fsp_update_fih(FSP_INFO_HEADER *fih)
 
 	fspr->fih = (uintptr_t)fih;
 }
+
+void soc_display_upd_value(const char *name, uint32_t size, uint64_t old,
+	uint64_t new)
+{
+	if (old == new) {
+		switch (size) {
+		case 1:
+			printk(BIOS_SPEW, "  0x%02llx: %s\n", new, name);
+			break;
+
+		case 2:
+			printk(BIOS_SPEW, "  0x%04llx: %s\n", new, name);
+			break;
+
+		case 4:
+			printk(BIOS_SPEW, "  0x%08llx: %s\n", new, name);
+			break;
+
+		case 8:
+			printk(BIOS_SPEW, "  0x%016llx: %s\n", new, name);
+			break;
+		}
+	} else {
+		switch (size) {
+		case 1:
+			printk(BIOS_SPEW, "  0x%02llx --> 0x%02llx: %s\n", old,
+				new, name);
+			break;
+
+		case 2:
+			printk(BIOS_SPEW, "  0x%04llx --> 0x%04llx: %s\n", old,
+				new, name);
+			break;
+
+		case 4:
+			printk(BIOS_SPEW, "  0x%08llx --> 0x%08llx: %s\n", old,
+				new, name);
+			break;
+
+		case 8:
+			printk(BIOS_SPEW, "  0x%016llx --> 0x%016llx: %s\n",
+				old, new, name);
+			break;
+		}
+	}
+}

src/drivers/intel/fsp1_1/include/fsp/gop.h

@@ -23,7 +23,7 @@
 /* GOP support */
 #if IS_ENABLED(CONFIG_GOP_SUPPORT)
 
-#include <soc/intel/common/gma.h>
+#include <fsp/gma.h>
 
 const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len);
 

src/drivers/intel/fsp1_1/include/fsp/util.h

@@ -46,6 +46,8 @@ void *get_next_type_guid_hob(UINT16 type, const EFI_GUID *guid,
 	const void *hob_start);
 void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start);
 void *get_first_resource_hob(const EFI_GUID *guid);
+void soc_display_upd_value(const char *name, uint32_t size, uint64_t old,
+	uint64_t new);
 /*
  * Relocate FSP entire binary into ram. Returns < 0 on error, 0 on success.
  * The FSP source is pointed to by region_device and the relocation information

src/drivers/intel/fsp1_1/raminit.c

@@ -19,10 +19,10 @@
 
 #include <cbmem.h>
 #include <console/console.h>
+#include <fsp/memmap.h>
 #include <fsp/util.h>
 #include <lib.h> /* hexdump */
 #include <reset.h>
-#include <soc/intel/common/memmap.h>
 #include <soc/pei_data.h>
 #include <soc/romstage.h>
 #include <string.h>

src/drivers/intel/fsp1_1/ramstage.c

@@ -22,10 +22,10 @@
 #include <cbmem.h>
 #include <cbfs.h>
 #include <console/console.h>
+#include <fsp/memmap.h>
+#include <fsp/ramstage.h>
 #include <fsp/util.h>
 #include <lib.h>
-#include <soc/intel/common/memmap.h>
-#include <soc/intel/common/ramstage.h>
 #include <stage_cache.h>
 #include <string.h>
 #include <timestamp.h>

src/drivers/intel/fsp1_1/romstage.c

@@ -66,10 +66,7 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
 	/* Display parameters */
 	printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
 		CONFIG_MMCONF_BASE_ADDRESS);
-	printk(BIOS_INFO, "Using: %s\n",
-		IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) ? "FSP 1.1" :
-		(IS_ENABLED(CONFIG_HAVE_MRC) ? "MRC" :
-		"No Memory Support"));
+	printk(BIOS_INFO, "Using FSP 1.1");
 
 	/* Display FSP banner */
 	print_fsp_info(fih);

src/drivers/intel/fsp1_1/stack.c

@@ -21,10 +21,10 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
-#include "memmap.h"
-#include "romstage.h"
+#include <fsp/memmap.h>
+#include <fsp/romstage.h>
+#include <fsp/stack.h>
 #include <soc/intel/common/util.h>
-#include "stack.h"
 #include <stdlib.h>
 
 const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE;

src/drivers/intel/fsp1_1/stage_cache.c

@@ -19,7 +19,7 @@
  */
 
 #include <console/console.h>
-#include <soc/intel/common/memmap.h>
+#include <fsp/memmap.h>
 #include <stage_cache.h>
 
 void stage_cache_external_region(void **base, size_t *size)

src/drivers/intel/fsp1_1/vbt.c

@@ -20,9 +20,9 @@
 
 #include <cbfs.h>
 #include <console/console.h>
+#include <fsp/ramstage.h>
 #include <fsp/util.h>
 #include <lib.h>
-#include <soc/intel/common/ramstage.h>
 #include <string.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 

src/soc/intel/braswell/Kconfig

@@ -17,6 +17,10 @@ config CPU_SPECIFIC_OPTIONS
 	select COLLECT_TIMESTAMPS
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+	select FSP_RAM_INIT
+	select FSP_ROMSTAGE
+	select FSP_STACK
+	select FSP_STAGE_CACHE
 	select HAS_PRECBMEM_TIMESTAMP_REGION
 	select HAVE_MONOTONIC_TIMER
 	select HAVE_SMI_HANDLER
@@ -33,11 +37,7 @@ config CPU_SPECIFIC_OPTIONS
 	select REG_SCRIPT
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
-	select SOC_INTEL_COMMON_FSP_RAM_INIT
-	select SOC_INTEL_COMMON_FSP_ROMSTAGE
 	select SOC_INTEL_COMMON_RESET
-	select SOC_INTEL_COMMON_STACK
-	select SOC_INTEL_COMMON_STAGE_CACHE
 	select SMM_TSEG
 	select SMP
 	select SPI_FLASH

src/soc/intel/braswell/cpu.c

@@ -28,7 +28,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
-#include <soc/intel/common/memmap.h>
+#include <fsp/memmap.h>
 #include <reg_script.h>
 #include <soc/iosf.h>
 #include <soc/msr.h>

src/soc/intel/braswell/include/soc/acpi.h

@@ -25,7 +25,7 @@
 #include <soc/nvs.h>
 
 #if CONFIG_GOP_SUPPORT
-#include <soc/intel/common/gma.h>
+#include <fsp/gma.h>
 int init_igd_opregion(igd_opregion_t *igd_opregion);
 #endif
 

src/soc/intel/braswell/include/soc/ramstage.h

@@ -23,7 +23,7 @@
 
 #include <chip.h>
 #include <device/device.h>
-#include <soc/intel/common/ramstage.h>
+#include <fsp/ramstage.h>
 
 /*
  * The soc_init_pre_device() function is called prior to device

src/soc/intel/braswell/include/soc/romstage.h

@@ -23,10 +23,10 @@
 
 #include <stdint.h>
 #include <arch/cpu.h>
+#include <fsp/romstage.h>
 #include <fsp/util.h>
 #include <soc/pei_data.h>
 #include <soc/pm.h>
-#include <soc/intel/common/romstage.h>
 
 void gfx_init(void);
 void tco_disable(void);

src/soc/intel/braswell/memmap.c

@@ -21,7 +21,7 @@
 #include <arch/io.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include <soc/intel/common/memmap.h>
+#include <fsp/memmap.h>
 #include <soc/iosf.h>
 #include <soc/smm.h>
 

src/soc/intel/braswell/northcluster.c

@@ -25,8 +25,8 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <fsp/memmap.h>
 #include <fsp/util.h>
-#include <soc/intel/common/memmap.h>
 #include <soc/iomap.h>
 #include <soc/iosf.h>
 #include <soc/pci_devs.h>

src/soc/intel/braswell/ramstage.c

@@ -40,7 +40,6 @@
 #include <soc/pm.h>
 #include <soc/ramstage.h>
 #include <soc/intel/common/acpi.h>
-#include <soc/intel/common/ramstage.h>
 #include <boardid.h>
 #include <stdlib.h>
 

src/soc/intel/common/Kconfig

@@ -40,35 +40,10 @@ config DISPLAY_SMM_MEMORY_MAP
 	bool "SMM: Display the SMM memory map"
 	default n
 
-config SOC_INTEL_COMMON_FSP_RAM_INIT
-	bool "FSP: Use the common raminit.c module"
-	default n
-	depends on PLATFORM_USES_FSP1_1
-
-config SOC_INTEL_COMMON_FSP_ROMSTAGE
-	bool
-	default n
-	depends on PLATFORM_USES_FSP1_1
-
 config SOC_INTEL_COMMON_RESET
 	bool
 	default n
 
-config SOC_INTEL_COMMON_STACK
-	bool
-	default n
-	depends on PLATFORM_USES_FSP1_1
-
-config SOC_INTEL_COMMON_STAGE_CACHE
-	bool
-	default n
-	depends on PLATFORM_USES_FSP1_1
-
-config ROMSTAGE_RAM_STACK_SIZE
-	hex "Size of the romstage RAM stack in bytes"
-	default 0x5000
-	depends on SOC_INTEL_COMMON_STACK
-
 config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	bool
 	default n

src/soc/intel/common/Makefile.inc

@@ -3,21 +3,14 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y)
 verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
 
 romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
-romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_RAM_INIT) += raminit.c
 romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
-romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_ROMSTAGE) += romstage.c
-romstage-$(CONFIG_SOC_INTEL_COMMON_STACK) += stack.c
-romstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c
-romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c
+romstage-y += util.c
 
-ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_ramstage.c
 ramstage-y += hda_verb.c
 ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
 ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
-ramstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c
-ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c
-ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c
+ramstage-y += util.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c
 
 # Create and add the MRC cache to the cbfs image

src/soc/intel/common/util.c

@@ -24,52 +24,6 @@
 #include <soc/intel/common/util.h>
 #include <stddef.h>
 
-void soc_display_upd_value(const char *name, uint32_t size, uint64_t old,
-	uint64_t new)
-{
-	if (old == new) {
-		switch (size) {
-		case 1:
-			printk(BIOS_SPEW, "  0x%02llx: %s\n", new, name);
-			break;
-
-		case 2:
-			printk(BIOS_SPEW, "  0x%04llx: %s\n", new, name);
-			break;
-
-		case 4:
-			printk(BIOS_SPEW, "  0x%08llx: %s\n", new, name);
-			break;
-
-		case 8:
-			printk(BIOS_SPEW, "  0x%016llx: %s\n", new, name);
-			break;
-		}
-	} else {
-		switch (size) {
-		case 1:
-			printk(BIOS_SPEW, "  0x%02llx --> 0x%02llx: %s\n", old,
-				new, name);
-			break;
-
-		case 2:
-			printk(BIOS_SPEW, "  0x%04llx --> 0x%04llx: %s\n", old,
-				new, name);
-			break;
-
-		case 4:
-			printk(BIOS_SPEW, "  0x%08llx --> 0x%08llx: %s\n", old,
-				new, name);
-			break;
-
-		case 8:
-			printk(BIOS_SPEW, "  0x%016llx --> 0x%016llx: %s\n",
-				old, new, name);
-			break;
-		}
-	}
-}
-
 uint32_t soc_get_variable_mtrr_count(uint64_t *msr)
 {
 	union {

src/soc/intel/common/util.h

@@ -24,8 +24,6 @@
 #include <stdint.h>
 
 asmlinkage void soc_display_mtrrs(void);
-void soc_display_upd_value(const char *name, uint32_t size, uint64_t old,
-	uint64_t new);
 uint32_t soc_get_variable_mtrr_count(uint64_t *msr);
 
 #endif /* _INTEL_COMMON_UTIL_H_ */

src/soc/intel/skylake/Kconfig

@@ -19,6 +19,10 @@ config CPU_SPECIFIC_OPTIONS
 	select COLLECT_TIMESTAMPS
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select CPU_MICROCODE_IN_CBFS
+	select FSP_RAM_INIT
+	select FSP_ROMSTAGE
+	select FSP_STACK
+	select FSP_STAGE_CACHE
 	select GENERIC_GPIO_LIB
 	select HAS_PRECBMEM_TIMESTAMP_REGION
 	select HAVE_HARD_RESET
@@ -39,11 +43,7 @@ config CPU_SPECIFIC_OPTIONS
 	select RELOCATABLE_RAMSTAGE
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
-	select SOC_INTEL_COMMON_FSP_RAM_INIT
-	select SOC_INTEL_COMMON_FSP_ROMSTAGE
 	select SOC_INTEL_COMMON_RESET
-	select SOC_INTEL_COMMON_STACK
-	select SOC_INTEL_COMMON_STAGE_CACHE
 	select SMM_MODULES
 	select SMM_TSEG
 	select SMP

src/soc/intel/skylake/include/soc/ramstage.h

@@ -23,7 +23,7 @@
 
 #include <chip.h>
 #include <device/device.h>
-#include <soc/intel/common/ramstage.h>
+#include <fsp/ramstage.h>
 
 void pch_enable_dev(device_t dev);
 void soc_init_pre_device(void *chip_info);

src/soc/intel/skylake/include/soc/romstage.h

@@ -21,7 +21,7 @@
 #ifndef _SOC_ROMSTAGE_H_
 #define _SOC_ROMSTAGE_H_
 
-#include <soc/intel/common/romstage.h>
+#include <fsp/romstage.h>
 
 struct chipset_power_state;
 struct chipset_power_state *fill_power_state(void);

src/soc/intel/skylake/include/soc/smm.h

@@ -23,8 +23,8 @@
 
 #include <stdint.h>
 #include <cpu/x86/msr.h>
-#include <soc/intel/common/romstage.h>
-#include <soc/intel/common/memmap.h>
+#include <fsp/memmap.h>
+#include <fsp/romstage.h>
 #include <soc/gpio.h>
 
 struct ied_header {

src/soc/intel/skylake/ramstage.c

@@ -19,7 +19,6 @@
  */
 
 #include <soc/ramstage.h>
-#include <soc/intel/common/ramstage.h>
 
 void soc_init_pre_device(void *chip_info)
 {