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nb/intel/ironlake: Remove unused structs 

These were copied from gm45, but are not used. Drop them.

Change-Id: I85ca37516272a2c1af88a65df2682e92d7579050
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Angel Pons 2020-06-22 17:12:16 +02:00 committed by Patrick Georgi
parent ec5b71ae30
commit 94dfaad725
1 changed files with 0 additions and 32 deletions
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32
src/northbridge/intel/ironlake/ironlake.h
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@ -3,38 +3,6 @@
#ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__
#define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ #define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__
#ifndef __ASSEMBLER__
typedef struct {
unsigned int CAS;
unsigned int tRAS;
unsigned int tRP;
unsigned int tRCD;
unsigned int tRFC;
unsigned int tWR;
unsigned int tRD;
unsigned int tRRD;
unsigned int tFAW;
unsigned int tWL;
} timings_t;
/* The setup is one DIMM per channel, so there's no need to find a
common timing setup between multiple chips (but chip and controller
still need to be coordinated */
typedef struct {
int txt_enabled;
int cores;
int max_ddr2_mhz;
int max_ddr3_mt;
int max_fsb_mhz;
int max_render_mhz;
int spd_type;
timings_t selected_timings;
} sysinfo_t;
#endif
#define DEFAULT_HECIBAR ((u8 *)0xfed17000) #define DEFAULT_HECIBAR ((u8 *)0xfed17000)