snow: use bootblock build class for I2C code
This gets rid of a bunch of duplicate I2C code in the bootblock. Change-Id: I51f625a0f738cca4ed2453fbcb78092e4110bc7e Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2289 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
David Hendricks
Ronald G. Minnich
parent
00e480e22d
commit
94e230aa93
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@ -1,4 +1,5 @@
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bootblock-y += pwm.c
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bootblock-y += pwm.c
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bootblock-y += s3c24x0_i2c.c
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bootblock-y += s5p_gpio.c
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bootblock-y += s5p_gpio.c
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bootblock-y += timer.c
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bootblock-y += timer.c
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@ -68,76 +68,7 @@ static void do_serial(void)
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uart_init();
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uart_init();
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}
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}
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#define I2C_WRITE 0
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#define I2C_READ 1
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#define I2C_OK 0
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#define I2C_NOK 1
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#define I2C_NACK 2
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#define I2C_NOK_LA 3 /* Lost arbitration */
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#define I2C_NOK_TOUT 4 /* time out */
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#define I2CSTAT_BSY 0x20 /* Busy bit */
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#define I2CSTAT_NACK 0x01 /* Nack bit */
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#define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
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#define I2CCON_IRPND 0x10 /* Interrupt pending bit */
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#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
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#define I2C_MODE_MR 0x80 /* Master Receive Mode */
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#define I2C_START_STOP 0x20 /* START / STOP */
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#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
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/* The timeouts we live by */
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enum {
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I2C_XFER_TIMEOUT_MS = 35, /* xfer to complete */
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I2C_INIT_TIMEOUT_MS = 1000, /* bus free on init */
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I2C_IDLE_TIMEOUT_MS = 100, /* waiting for bus idle */
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I2C_STOP_TIMEOUT_US = 200, /* waiting for stop events */
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};
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#define I2C0_BASE 0x12c60000
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#define I2C0_BASE 0x12c60000
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struct s3c24x0_i2c_bus i2c0 = {
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.node = 0,
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.bus_num = 0,
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.regs = (struct s3c24x0_i2c *)I2C0_BASE,
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.id = PERIPH_ID_I2C0,
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};
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static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
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{
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unsigned long freq, pres = 16, div;
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freq = clock_get_periph_rate(PERIPH_ID_I2C0);
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/* calculate prescaler and divisor values */
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if ((freq / pres / (16 + 1)) > speed)
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/* set prescaler to 512 */
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pres = 512;
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div = 0;
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while ((freq / pres / (div + 1)) > speed)
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div++;
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/* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
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writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
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/* init to SLAVE REVEIVE and set slaveaddr */
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writel(0, &i2c->iicstat);
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writel(slaveadd, &i2c->iicadd);
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/* program Master Transmit (and implicit STOP) */
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writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
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}
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static void i2c_bus_init(struct s3c24x0_i2c_bus *i2c, unsigned int bus)
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{
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// exynos_pinmux_config(i2c->id, 0);
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gpio_cfg_pin(GPIO_B30, EXYNOS_GPIO_FUNC(0x2));
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gpio_cfg_pin(GPIO_B31, EXYNOS_GPIO_FUNC(0x2));
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gpio_set_pull(GPIO_B30, EXYNOS_GPIO_PULL_NONE);
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gpio_set_pull(GPIO_B31, EXYNOS_GPIO_PULL_NONE);
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i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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}
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void do_barriers(void);
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void do_barriers(void);
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void do_barriers(void)
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void do_barriers(void)
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@ -170,338 +101,6 @@ void my_udelay(unsigned int n)
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"bne 1b":"=r" (n):"0"(n));
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"bne 1b":"=r" (n):"0"(n));
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}
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}
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void i2c_init(int speed, int slaveadd)
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{
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struct s3c24x0_i2c_bus *i2c = &i2c0;
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struct exynos5_gpio_part1 *gpio;
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int i;
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uint32_t x;
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#if 0
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/* By default i2c channel 0 is the current bus */
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g_current_bus = 0;
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i2c = get_bus(g_current_bus);
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if (!i2c)
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return;
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#endif
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i2c_bus_init(i2c, 0);
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/* wait for some time to give previous transfer a chance to finish */
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i = I2C_INIT_TIMEOUT_MS * 20;
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while ((readl(&i2c->regs->iicstat) & I2CSTAT_BSY) && (i > 0)) {
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my_udelay(50);
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i--;
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}
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gpio = (struct exynos5_gpio_part1 *)(EXYNOS5_GPIO_PART1_BASE);
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/* FIXME(dhendrix): cannot use nested macro (compilation failure) */
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// writel((readl(&gpio->b3.con) & ~0x00FF) | 0x0022, &gpio->b3.con);
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x = readl(&gpio->b3.con);
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writel((x & ~0x00FF) | 0x0022, &gpio->b3.con);
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i2c_ch_init(i2c->regs, speed, slaveadd);
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}
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static int WaitForXfer(struct s3c24x0_i2c *i2c)
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{
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int i;
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i = I2C_XFER_TIMEOUT_MS * 20;
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while (!(readl(&i2c->iiccon) & I2CCON_IRPND)) {
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if (i == 0) {
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//debug("%s: i2c xfer timeout\n", __func__);
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return I2C_NOK_TOUT;
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}
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my_udelay(50);
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i--;
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}
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return I2C_OK;
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}
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static int IsACK(struct s3c24x0_i2c *i2c)
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{
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return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
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}
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static void ReadWriteByte(struct s3c24x0_i2c *i2c)
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{
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uint32_t x;
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x = readl(&i2c->iiccon);
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writel(x & ~I2CCON_IRPND, &i2c->iiccon);
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/* FIXME(dhendrix): cannot use nested macro (compilation failure) */
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// writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
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}
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/*
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* Verify the whether I2C ACK was received or not
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*
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* @param i2c pointer to I2C register base
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* @param buf array of data
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* @param len length of data
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* return I2C_OK when transmission done
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* I2C_NACK otherwise
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*/
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static int i2c_send_verify(struct s3c24x0_i2c *i2c, unsigned char buf[],
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unsigned char len)
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{
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int i, result = I2C_OK;
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if (IsACK(i2c)) {
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for (i = 0; (i < len) && (result == I2C_OK); i++) {
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writel(buf[i], &i2c->iicds);
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ReadWriteByte(i2c);
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result = WaitForXfer(i2c);
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if (result == I2C_OK && !IsACK(i2c))
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result = I2C_NACK;
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}
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} else {
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result = I2C_NACK;
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}
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return result;
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}
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/*
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* Send a STOP event and wait for it to have completed
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*
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* @param mode If it is a master transmitter or receiver
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* @return I2C_OK if the line became idle before timeout I2C_NOK_TOUT otherwise
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*/
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static int i2c_send_stop(struct s3c24x0_i2c *i2c, int mode)
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{
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int timeout;
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/* Setting the STOP event to fire */
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writel(mode | I2C_TXRX_ENA, &i2c->iicstat);
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ReadWriteByte(i2c);
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/* Wait for the STOP to send and the bus to go idle */
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for (timeout = I2C_STOP_TIMEOUT_US; timeout > 0; timeout -= 5) {
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if (!(readl(&i2c->iicstat) & I2CSTAT_BSY))
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return I2C_OK;
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my_udelay(5);
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}
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return I2C_NOK_TOUT;
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}
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/*
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* cmd_type is 0 for write, 1 for read.
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*
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* addr_len can take any value from 0-255, it is only limited
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* by the char, we could make it larger if needed. If it is
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* 0 we skip the address write cycle.
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*/
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static int i2c_transfer(struct s3c24x0_i2c *i2c,
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unsigned char cmd_type,
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unsigned char chip,
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unsigned char addr[],
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unsigned char addr_len,
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unsigned char data[],
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unsigned short data_len)
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{
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int i, result, stop_bit_result;
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uint32_t x;
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if (data == 0 || data_len == 0) {
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/* Don't support data transfer of no length or to address 0 */
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//debug("i2c_transfer: bad call\n");
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return I2C_NOK;
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}
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/* Check I2C bus idle */
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i = I2C_IDLE_TIMEOUT_MS * 20;
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while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
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my_udelay(50);
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i--;
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}
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if (readl(&i2c->iicstat) & I2CSTAT_BSY) {
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//debug("%s: bus busy\n", __func__);
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return I2C_NOK_TOUT;
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}
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/* FIXME(dhendrix): cannot use nested macro (compilation failure) */
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//writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
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x = readl(&i2c->iiccon);
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writel(x | I2CCON_ACKGEN, &i2c->iiccon);
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if (addr && addr_len) {
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writel(chip, &i2c->iicds);
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/* send START */
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writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
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&i2c->iicstat);
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if (WaitForXfer(i2c) == I2C_OK)
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result = i2c_send_verify(i2c, addr, addr_len);
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else
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result = I2C_NACK;
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} else
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result = I2C_NACK;
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switch (cmd_type) {
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case I2C_WRITE:
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if (result == I2C_OK)
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result = i2c_send_verify(i2c, data, data_len);
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else {
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writel(chip, &i2c->iicds);
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/* send START */
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writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
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&i2c->iicstat);
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if (WaitForXfer(i2c) == I2C_OK)
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result = i2c_send_verify(i2c, data, data_len);
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}
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if (result == I2C_OK)
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result = WaitForXfer(i2c);
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stop_bit_result = i2c_send_stop(i2c, I2C_MODE_MT);
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break;
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case I2C_READ:
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{
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int was_ok = (result == I2C_OK);
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writel(chip, &i2c->iicds);
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/* resend START */
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writel(I2C_MODE_MR | I2C_TXRX_ENA |
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I2C_START_STOP, &i2c->iicstat);
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ReadWriteByte(i2c);
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result = WaitForXfer(i2c);
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if (was_ok || IsACK(i2c)) {
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i = 0;
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while ((i < data_len) && (result == I2C_OK)) {
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/* disable ACK for final READ */
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if (i == data_len - 1) {
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/* FIXME(dhendrix): nested macro */
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#if 0
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writel(readl(&i2c->iiccon) &
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~I2CCON_ACKGEN,
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&i2c->iiccon);
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#endif
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x = readl(&i2c->iiccon) & ~I2CCON_ACKGEN;
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writel(x, &i2c->iiccon);
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}
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ReadWriteByte(i2c);
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result = WaitForXfer(i2c);
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data[i] = readl(&i2c->iicds);
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i++;
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}
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} else {
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result = I2C_NACK;
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}
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stop_bit_result = i2c_send_stop(i2c, I2C_MODE_MR);
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break;
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}
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default:
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//debug("i2c_transfer: bad call\n");
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result = stop_bit_result = I2C_NOK;
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break;
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}
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/*
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* If the transmission went fine, then only the stop bit was left to
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* fail. Otherwise, the real failure we're interested in came before
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* that, during the actual transmission.
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*/
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return (result == I2C_OK) ? stop_bit_result : result;
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}
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int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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struct s3c24x0_i2c_bus *i2c = &i2c0;
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uchar xaddr[4];
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int ret;
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if (alen > 4) {
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//debug("I2C read: addr len %d not supported\n", alen);
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return 1;
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}
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if (alen > 0) {
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xaddr[0] = (addr >> 24) & 0xFF;
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xaddr[1] = (addr >> 16) & 0xFF;
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xaddr[2] = (addr >> 8) & 0xFF;
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xaddr[3] = addr & 0xFF;
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}
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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/*
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* EEPROM chips that implement "address overflow" are ones
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* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
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* address and the extra bits end up in the "chip address"
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* bit slots. This makes a 24WC08 (1Kbyte) chip look like
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* four 256 byte chips.
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||||||
*
|
|
||||||
* Note that we consider the length of the address field to
|
|
||||||
* still be one byte because the extra address bits are
|
|
||||||
* hidden in the chip address.
|
|
||||||
*/
|
|
||||||
if (alen > 0)
|
|
||||||
chip |= ((addr >> (alen * 8)) &
|
|
||||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
|
||||||
#endif
|
|
||||||
if (!i2c)
|
|
||||||
return -1;
|
|
||||||
ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, &xaddr[4 - alen],
|
|
||||||
alen, buffer, len);
|
|
||||||
if (ret) {
|
|
||||||
//debug("I2c read: failed %d\n", ret);
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
|
||||||
{
|
|
||||||
struct s3c24x0_i2c_bus *i2c;
|
|
||||||
uchar xaddr[4];
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
if (alen > 4) {
|
|
||||||
//debug("I2C write: addr len %d not supported\n", alen);
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (alen > 0) {
|
|
||||||
xaddr[0] = (addr >> 24) & 0xFF;
|
|
||||||
xaddr[1] = (addr >> 16) & 0xFF;
|
|
||||||
xaddr[2] = (addr >> 8) & 0xFF;
|
|
||||||
xaddr[3] = addr & 0xFF;
|
|
||||||
}
|
|
||||||
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
|
|
||||||
/*
|
|
||||||
* EEPROM chips that implement "address overflow" are ones
|
|
||||||
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
|
||||||
* address and the extra bits end up in the "chip address"
|
|
||||||
* bit slots. This makes a 24WC08 (1Kbyte) chip look like
|
|
||||||
* four 256 byte chips.
|
|
||||||
*
|
|
||||||
* Note that we consider the length of the address field to
|
|
||||||
* still be one byte because the extra address bits are
|
|
||||||
* hidden in the chip address.
|
|
||||||
*/
|
|
||||||
if (alen > 0)
|
|
||||||
chip |= ((addr >> (alen * 8)) &
|
|
||||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
|
||||||
#endif
|
|
||||||
//i2c = get_bus(g_current_bus);
|
|
||||||
i2c = &i2c0;
|
|
||||||
if (!i2c)
|
|
||||||
return -1;
|
|
||||||
ret = i2c_transfer(i2c->regs, I2C_WRITE, chip << 1, &xaddr[4 - alen],
|
|
||||||
alen, buffer, len);
|
|
||||||
|
|
||||||
return ret != 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Max77686 parameters values
|
* Max77686 parameters values
|
||||||
* see max77686.h for parameters details
|
* see max77686.h for parameters details
|
||||||
|
|
@ -1428,6 +1027,7 @@ void bootblock_mainboard_init(void)
|
||||||
{
|
{
|
||||||
/* FIXME: we should not need UART in bootblock, this is only
|
/* FIXME: we should not need UART in bootblock, this is only
|
||||||
done for testing purposes */
|
done for testing purposes */
|
||||||
|
i2c_set_early_reg(I2C0_BASE);
|
||||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||||
power_init();
|
power_init();
|
||||||
clock_init();
|
clock_init();
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue