soc/amd/stoneyridge: Enable early cbmem
Add a memmap file with a cbmem_top() function. Remove the LATE_CBMEM_INIT, allowing the default of EARLY. Remove calls to the late-only set_top_of_ram() function. Change-Id: I11ad7190031c912642a7312f2fc6f792866288b7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -35,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_USBDEBUG_OPTIONS
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select HAVE_USBDEBUG_OPTIONS
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select HAVE_HARD_RESET
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select HAVE_HARD_RESET
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select LAPIC_MONOTONIC_TIMER
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select LAPIC_MONOTONIC_TIMER
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select LATE_CBMEM_INIT
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select SPI_FLASH if HAVE_ACPI_RESUME
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select SPI_FLASH if HAVE_ACPI_RESUME
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select TSC_SYNC_LFENCE
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select TSC_SYNC_LFENCE
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select SOC_AMD_COMMON
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select SOC_AMD_COMMON
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@ -15,6 +15,8 @@
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#include <stdint.h>
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#include <stdint.h>
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#include <arch/io.h>
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#include <arch/io.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <cbmem.h>
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#include <cbmem.h>
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#define CBMEM_TOP_SCRATCHPAD 0x78
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#define CBMEM_TOP_SCRATCHPAD 0x78
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@ -31,3 +33,13 @@ uintptr_t restore_top_of_low_cacheable(void)
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top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD);
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top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD);
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return (top_cache << 16);
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return (top_cache << 16);
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}
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}
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void *cbmem_top(void)
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{
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msr_t tom = rdmsr(TOP_MEM);
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if (!tom.lo)
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return 0;
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else
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return (void *)restore_top_of_low_cacheable();
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}
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