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Broadwell: Fix PCIe L1 Sub-State capability ID not filled. 

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 31d7276fbdca67937bcdf0d5c2af371a2fd1a510
Original-BUG=chrome-os-partner:31424,chromeos-os-partner:32380
Original-TEST=Build a BIOS image and check the value is applied correctly.
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Change-Id: I0adda3643776b259a635a021babd983090f1df43
Original-Reviewed-on: https://chromium-review.googlesource.com/220475
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: Id88c11ed128b44c3a60ef1a141b99071c1ee15d3
Reviewed-on: http://review.coreboot.org/9267
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kenji Chen 2014-09-30 14:17:35 +08:00 committed by Patrick Georgi
parent e1ca8a3d42
commit 94fea491df
1 changed files with 4 additions and 1 deletions
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5
src/soc/intel/broadwell/pcie.c
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@ -558,9 +558,12 @@ static void pch_pcie_early(struct device *dev)
pcie_update_cfg8(dev, 0xf5, 0x0f, 0);
/* Set Extended Capability to offset 200h and Advanced Error Report. */
/* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001);
/* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
pcie_update_cfg(dev, 0x200, ~0xffff, 0x001e);
pcie_update_cfg(dev, 0x320, ~(3 << 20) & ~(7 << 6),
(1 << 20) | (3 << 6));
/* Enable Relaxed Order from Root Port. */