soc/intel/skylake: Drop always-zero PowerLimit4 dt setting

Unset devicetree settings default to zero, so the devicetree setting can
be removed. Looks like no one needs it anyway.

Change-Id: Iad94538c5465347b37a99c6c9f20988168661593
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb

@@ -105,9 +105,6 @@ chip soc/intel/skylake
 		.tdp_pl2_override = 60,
 	}"
 
-	# Power Limit Related
-	register "PowerLimit4" = "0"
-
 	# Lock Down
 	register "common_soc_config" = "{
 	.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,

src/soc/intel/skylake/chip.c

@@ -303,7 +303,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
 	tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;
-	tconfig->PowerLimit4 = config->PowerLimit4;
+	tconfig->PowerLimit4 = 0;
 	/*
 	 * To disable HECI, the Psf needs to be left unlocked
 	 * by FSP till end of post sequence. Based on the devicetree

src/soc/intel/skylake/chip.h

@@ -87,9 +87,6 @@ struct soc_intel_skylake_config {
 	/* TCC activation offset */
 	uint32_t tcc_offset;
 
-	/* Package PL4 power limit in Watts */
-	u32 PowerLimit4;
-
 	/* Whether to ignore VT-d support of the SKU */
 	int ignore_vtd;