add some SPD values from specs. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -73,6 +73,7 @@
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#define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33 /* Command and address signal input hold time */
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#define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33 /* Command and address signal input hold time */
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#define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34 /* Data signal input setup time */
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#define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34 /* Data signal input setup time */
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#define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data signal input hold time */
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#define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data signal input hold time */
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#define SPD_WRITE_RECOVERY_TIME 36 /* Write recovery time (tWR) */
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#define SPD_SPD_DATA_REVISION_CODE 62 /* SPD data revision code */
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#define SPD_SPD_DATA_REVISION_CODE 62 /* SPD data revision code */
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#define SPD_CHECKSUM_FOR_BYTES_0_TO_62 63 /* Checksum for bytes 0-62 */
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#define SPD_CHECKSUM_FOR_BYTES_0_TO_62 63 /* Checksum for bytes 0-62 */
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#define SPD_MANUFACTURER_JEDEC_ID_CODE 64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */
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#define SPD_MANUFACTURER_JEDEC_ID_CODE 64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */
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@ -129,6 +130,11 @@
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#define SPD_CAS_LATENCY_3_5 0x20
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#define SPD_CAS_LATENCY_3_5 0x20
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#define SPD_CAS_LATENCY_4_0 0x40
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#define SPD_CAS_LATENCY_4_0 0x40
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#define SPD_CAS_LATENCY_DDR2_3 (1 << 3)
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#define SPD_CAS_LATENCY_DDR2_4 (1 << 4)
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#define SPD_CAS_LATENCY_DDR2_5 (1 << 5)
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#define SPD_CAS_LATENCY_DDR2_6 (1 << 6)
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/* SPD_SUPPORTED_BURST_LENGTHS values. */
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/* SPD_SUPPORTED_BURST_LENGTHS values. */
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#define SPD_BURST_LENGTH_1 1
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#define SPD_BURST_LENGTH_1 1
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#define SPD_BURST_LENGTH_2 2
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#define SPD_BURST_LENGTH_2 2
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