This patch unifies the socket_mPGA604_800Mhz and socket_mPGA604_533Mhz to a
combined socket_mPGA604. No other sockets come with clock rates, and there is no difference in code, except for the number of microcode patches included in a build. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
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da65fbf208
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953253f093
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@ -1,4 +1,5 @@
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config chip.h
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object socket_mPGA604_800Mhz.o
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object socket_mPGA604.o
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dir /cpu/intel/model_f2x
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dir /cpu/intel/model_f3x
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dir /cpu/intel/model_f4x
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@ -3,5 +3,5 @@
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struct chip_operations cpu_intel_socket_mPGA604_800Mhz_ops = {
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CHIP_NAME("Socket mPGA604 800Mhz CPU")
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CHIP_NAME("Socket mPGA604 CPU")
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};
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@ -1,3 +0,0 @@
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config chip.h
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object socket_mPGA604_533Mhz.o
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dir /cpu/intel/model_f2x
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@ -1,4 +0,0 @@
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extern struct chip_operations cpu_intel_socket_mPGA604_533Mhz_ops;
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struct cpu_intel_socket_mPGA604_533Mhz_config {
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};
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@ -1,7 +0,0 @@
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#include <device/device.h>
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#include "chip.h"
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struct chip_operations cpu_intel_socket_mPGA604_533Mhz_ops = {
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CHIP_NAME("Socket mPGA604 533Mhz CPU")
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};
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@ -193,10 +193,10 @@ chip northbridge/intel/e7520 # mch
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device pci 06.0 on end
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end
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device apic_cluster 0 on
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chip cpu/intel/socket_mPGA604_800Mhz # cpu 0
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chip cpu/intel/socket_mPGA604 # cpu 0
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device apic 0 on end
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end
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chip cpu/intel/socket_mPGA604_800Mhz # cpu 1
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chip cpu/intel/socket_mPGA604 # cpu 1
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device apic 6 on end
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end
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end
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@ -203,10 +203,10 @@ chip northbridge/intel/e7520
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end
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end
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device apic_cluster 0 on
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chip cpu/intel/socket_mPGA604_800Mhz # cpu 0
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chip cpu/intel/socket_mPGA604 # cpu 0
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device apic 0 on end
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end
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chip cpu/intel/socket_mPGA604_800Mhz # cpu 1
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chip cpu/intel/socket_mPGA604 # cpu 1
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device apic 6 on end
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end
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end
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@ -212,10 +212,10 @@ chip northbridge/intel/e7501
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end # SB
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end # PCI_DOMAIN
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device apic_cluster 0 on
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chip cpu/intel/socket_mPGA604_533Mhz
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chip cpu/intel/socket_mPGA604
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device apic 0 on end
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end
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chip cpu/intel/socket_mPGA604_533Mhz
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chip cpu/intel/socket_mPGA604
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device apic 6 on end
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end
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end
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@ -187,10 +187,10 @@ chip northbridge/intel/e7525 # mch
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device pci 08.0 on end
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end
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device apic_cluster 0 on
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chip cpu/intel/socket_mPGA604_800Mhz # cpu0
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chip cpu/intel/socket_mPGA604 # cpu0
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device apic 0 on end
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end
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chip cpu/intel/socket_mPGA604_800Mhz # cpu1
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chip cpu/intel/socket_mPGA604 # cpu1
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device apic 6 on end
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end
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end
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@ -210,10 +210,10 @@ chip northbridge/intel/e7520 # MCH
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end
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device apic_cluster 0 on
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chip cpu/intel/socket_mPGA604_800Mhz # CPU 0
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chip cpu/intel/socket_mPGA604 # CPU 0
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device apic 0 on end
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end
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chip cpu/intel/socket_mPGA604_800Mhz # CPU 1
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chip cpu/intel/socket_mPGA604 # CPU 1
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device apic 6 on end
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end
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end
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@ -210,10 +210,10 @@ chip northbridge/intel/e7520 # MCH
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end
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device apic_cluster 0 on
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chip cpu/intel/socket_mPGA604_800Mhz # CPU 0
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chip cpu/intel/socket_mPGA604 # CPU 0
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device apic 0 on end
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end
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chip cpu/intel/socket_mPGA604_800Mhz # CPU 1
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chip cpu/intel/socket_mPGA604 # CPU 1
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device apic 6 on end
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end
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end
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@ -206,10 +206,10 @@ chip northbridge/intel/e7520 # mch
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device pci 06.0 on end
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end
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device apic_cluster 0 on
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chip cpu/intel/socket_mPGA604_800Mhz # cpu 0
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chip cpu/intel/socket_mPGA604 # cpu 0
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device apic 0 on end
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end
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chip cpu/intel/socket_mPGA604_800Mhz # cpu 1
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chip cpu/intel/socket_mPGA604 # cpu 1
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device apic 6 on end
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end
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end
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@ -197,10 +197,10 @@ chip northbridge/intel/e7520 # mch
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device pci 06.0 on end
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end
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device apic_cluster 0 on
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chip cpu/intel/socket_mPGA604_800Mhz # cpu 0
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chip cpu/intel/socket_mPGA604 # cpu 0
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device apic 0 on end
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end
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chip cpu/intel/socket_mPGA604_800Mhz # cpu 1
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chip cpu/intel/socket_mPGA604 # cpu 1
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device apic 6 on end
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end
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end
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@ -172,10 +172,10 @@ chip northbridge/intel/e7501
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end # SB
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end # PCI_DOMAIN
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device apic_cluster 0 on
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chip cpu/intel/socket_mPGA604_533Mhz
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chip cpu/intel/socket_mPGA604
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device apic 0 on end
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end
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chip cpu/intel/socket_mPGA604_533Mhz
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chip cpu/intel/socket_mPGA604
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device apic 6 on end
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end
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end
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