mb/google/sarien: Add HD Audio verb table
Implement HD Audio verb table for RealTek ALC 3204/3254 codec on google sarien and arcada board. BUG=b:119058355,119054586 TEST=Confirm audio play back is working on Sarien and Arcada board. Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/29484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
This commit is contained in:
Lijian Zhao
Patrick Georgi
parent
5c9237fd5f
commit
95370e1f04
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@ -13,9 +13,10 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_I2C_TPM_CR50
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select MAINBOARD_HAS_TPM2
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select SOC_INTEL_COFFEELAKE
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select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
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select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK
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select SOC_INTEL_COFFEELAKE
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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@ -27,5 +27,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
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subdirs-y += variants/$(VARIANT_DIR)
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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@ -0,0 +1,16 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "variant/hda_verb.h"
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@ -0,0 +1,209 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef MAINBOARD_HDA_VERB_H
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#define MAINBOARD_HDA_VERB_H
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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/* coreboot specific header */
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0x10ec0295, // Codec Vendor / Device ID: Realtek ALC3204
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0xffffffff, // Subsystem ID
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0x0000002b, // Number of jacks (NID entries)
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/* Rest Codec First */
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AZALIA_RESET(0x1),
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/* NID 0x01, HDA Codec Subsystem ID Verb Table */
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AZALIA_SUBVENDOR(0x0, 0x102808b6),
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/* Pin Widget Verb Table */
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AZALIA_PIN_CFG(0x0, 0x12, 0xb7a60130),
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AZALIA_PIN_CFG(0x0, 0x13, 0x411111f0),
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AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
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AZALIA_PIN_CFG(0x0, 0x16, 0x40000000),
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AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
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AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
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AZALIA_PIN_CFG(0x0, 0x19, 0x04a11030),
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AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
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AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),
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AZALIA_PIN_CFG(0x0, 0x1d, 0x40c00001),
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AZALIA_PIN_CFG(0x0, 0x1e, 0x421212f2),
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AZALIA_PIN_CFG(0x0, 0x21, 0x04211020),
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/* D reset */
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0x0205003C,
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0x0204F254,
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0x0205003C,
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0x0204F214,
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/* JD1 - 2port JD mode */
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0x02050009,
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0x0204E003,
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0x0205000A,
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0x02047770,
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/* Set TRS type-1 */
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0x02050045,
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0x02045289,
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0x02050049,
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0x02040049,
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/* Set TRS type-2 + Set UAJ Line2 vref(ALC3254) */
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0x0205004A,
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0x0204A830,
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0x02050063,
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0x0204CF00,
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/* NID 0x20 set class-D to 2W@4ohm (+12dB gain)
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* + Set sine tone gain(0x34) */
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0x02050038,
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0x02043909,
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0x05C50000,
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0x05C43482,
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/* AGC-1 Disable + (Front Gain=0dB ) */
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0x05D50006,
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0x05D44C50,
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0x05D50002,
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0x05D44004,
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/* AGC-2 (Backt Boost Gain= -0.375dB ,Limiter = -3dB) */
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0x05D50003,
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0x05D45E5E,
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0x05D50001,
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0x05D4D788,
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/* AGC-3 + AGC Enable */
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0x05D50009,
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0x05D451FF,
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0x05D50006,
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0x05D44E50,
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/* HP-JD Enable +Nokia type */
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0x0205004A,
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0x02042010,
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0x02050008,
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0x02046A0C,
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/* EAPD set to verb-control + I2C Un-use+ DVDD3.3V */
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0x02050010,
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0x02040020,
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0x02050034,
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0x0204A23D,
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/* Class D silent detection Enable -84dB threshold */
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0x02050030,
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0x02049000,
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0x02050037,
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0x0204FE15,
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/* Disable EQ + set 250Hz 3rd High Pass filter */
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0x05350000,
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0x0534203A,
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0x05350000,
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0x0534203A,
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/* Left Channel-1 */
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0x0535001d,
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0x05340800,
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0x0535001e,
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0x05340800,
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/* Left Channel-2 */
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0x05350003,
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0x05341EF8,
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0x05350004,
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0x05340000,
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/* Left Channel-3 */
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0x05350005,
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0x053403EE,
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0x05350006,
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0x0534FA60,
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/* Left Channel-4 */
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0x05350007,
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0x05341E10,
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0x05350008,
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0x05347B86,
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/* Left Channel-5 */
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0x05350009,
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0x053401F7,
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0x0535000A,
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0x05349FB6,
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/* Left Channel-6 */
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0x0535000B,
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0x05341C00,
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0x0535000C,
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0x05340000,
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/* Left Channel-7 */
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0x0535000D,
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0x05340200,
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0x0535000E,
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0x05340000,
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/* Right Channel-1 */
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0x05450000,
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0x05442000,
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0x0545001d,
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0x05440800,
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/* Right Channel-2 */
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0x0545001e,
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0x05440800,
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0x05450003,
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0x05441EF8,
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/* Right Channel-3 */
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0x05450004,
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0x05440000,
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0x05450005,
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0x054403EE,
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/* Right Channel-4 */
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0x05450006,
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0x0544FA60,
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0x05450007,
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0x05441E10,
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/* Right Channel-5 */
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0x05450008,
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0x05447B86,
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0x05450009,
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0x054401F7,
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/* Right Channel-6 */
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0x0545000A,
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0x05449FB6,
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0x0545000B,
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0x05441C00,
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/* Right Channel-7 */
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0x0545000C,
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0x05440000,
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0x0545000D,
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0x05440200,
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/* Right Channel-8 + EQ Update & Enable */
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0x0545000E,
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0x05440000,
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0x05350000,
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0x0534E03A,
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/* Enable all Microphone */
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0x0205000D,
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0x0204A023,
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0x0205000D,
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0x0204A023,
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/* Enable Internal Speaker (NID14) */
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0x0205000F,
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0x02040000,
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0x0205000F,
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0x02040000,
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};
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const u32 pc_beep_verbs[] = {
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/* PCBeep pass through to NID14 for ePSA test-1 */
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0x02050036,
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0x020477D7,
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0x0143B000,
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0x01470740,
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/* PCBeep pass through to NID14 for ePSA test-2 */
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0x01470C02,
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0x01470C02,
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0x01470C02,
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0x01470C02,
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};
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AZALIA_ARRAY_SIZES;
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#endif
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@ -0,0 +1,152 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef MAINBOARD_HDA_VERB_H
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#define MAINBOARD_HDA_VERB_H
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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/* coreboot specific header */
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0x10ec0236, // Codec Vendor / Device ID: Realtek ALC3204
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0xffffffff, // Subsystem ID
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0x0000001e, // Number of jacks (NID entries)
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/* Rest Codec First */
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AZALIA_RESET(0x1),
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/* NID 0x01, HDA Codec Subsystem ID Verb Table */
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AZALIA_SUBVENDOR(0x0, 0x102808b8),
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/* Pin Widget Verb Table */
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AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140),
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AZALIA_PIN_CFG(0x0, 0x13, 0x40000000),
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AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
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AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
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AZALIA_PIN_CFG(0x0, 0x19, 0x02a11030),
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AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
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AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),
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AZALIA_PIN_CFG(0x0, 0x1d, 0x40700001),
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AZALIA_PIN_CFG(0x0, 0x1e, 0x421212f2),
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AZALIA_PIN_CFG(0x0, 0x21, 0x02211020),
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/* ALC3204 default-1 */
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0x02050040,
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0x02049800,
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0x02050034,
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0x0204023C,
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/* ALC3204 default-2 */
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0x0205003C,
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0x02040354,
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0x0205003C,
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0x02040314,
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/* ALC3204 Speaker output power - 4 ohm 2W (+12dB gain)
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* + Combo Jack TRS setting */
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0x02050038,
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0x02043901,
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0x02050045,
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0x02045089,
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/* H/W AGC setting-1 */
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0x02050016,
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0x02040C50,
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0x02050012,
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0x0204EBC2,
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/* H/W AGC setting-2 */
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0x02050013,
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0x0204401D,
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0x02050016,
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0x02044E50,
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/* Zero data + EAPD to verb-control */
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0x02050037,
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0x0204FE15,
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0x02050010,
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0x02040020,
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/* Zero data */
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0x02050030,
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0x02048000,
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0x02050030,
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0x02048000,
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/* ALC3204 default-3 */
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0x05750003,
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0x05740DA3,
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0x02050046,
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0x02040004,
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/* ALC3204 default-4 */
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0x0205001B,
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0x02040A4B,
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0x02050008,
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0x02046A6C,
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/* JD1 */
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0x02050009,
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0x0204E003,
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0x0205000A,
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0x02047770,
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/* Microphone + Array MIC security Disable +ADC clock Enable */
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0x0205000D,
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0x0204A020,
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0x02050005,
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0x02040700,
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/* Speaker Enable */
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0x0205000C,
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0x020401EF,
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0x0205000C,
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0x020401EF,
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/* EQ Bypass + EQ HPF cutoff 250Hz */
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0x05350000,
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0x0534201A,
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0x0535001d,
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0x05340800,
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/* EQ-2 */
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0x0535001e,
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0x05340800,
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0x05350003,
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0x05341EF8,
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/* EQ-3 */
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0x05350004,
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0x05340000,
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0x05450000,
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0x05442000,
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/* EQ-4 */
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0x0545001d,
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0x05440800,
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0x0545001e,
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0x05440800,
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/* EQ-5 */
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0x05450003,
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0x05441EF8,
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0x05450004,
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0x05440000,
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/* EQ Update */
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0x05350000,
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0x0534E01A,
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0x05350000,
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0x0534E01A,
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};
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const u32 pc_beep_verbs[] = {
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/* PCBeep pass through to NID14 for ePSA test-1 */
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0x02050036,
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0x02047717,
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0x02050036,
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0x02047717,
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/* PCBeep pass through to NID14 for ePSA test-2 */
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0x01470740,
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0x0143B000,
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0x01470C02,
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0x01470C02,
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};
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AZALIA_ARRAY_SIZES;
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#endif
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