soc/intel/tigerlake: Update ACPI files
Add and update ACPI files for Tiger Lake SoC Use ASL2.0 code syntax for new acpi(camera_clock_ctl.asl) Reference PCH EDS#576591 vol1 rev1.2 PCH EDS#575857 vol2 rev1.0 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ib82156830273c2937f5f02713ed7dd27da41c857 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37781 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ravi Sarawadi
Patrick Georgi
parent
69855f2e60
commit
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2020 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define R_ICLK_PCR_CAMERA1 0x8000
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#define B_ICLK_PCR_FREQUENCY 0x1
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#define B_ICLK_PCR_REQUEST 0x2
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Scope (\_SB.PCI0) {
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/* IsCLK PCH register for clock settings */
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OperationRegion (ICLK, SystemMemory, PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1, 0x40)
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Field (ICLK, AnyAcc, Lock, Preserve)
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{
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CLK1, 8,
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Offset(0x0C),
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CLK2, 8,
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Offset(0x18),
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CLK3, 8,
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Offset(0x24),
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CLK4, 8,
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Offset(0x30),
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CLK5, 8,
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Offset(0x3C),
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CLK6, 8,
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}
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/*
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* Helper function for Read And OR Write
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* Arg0 : source and destination
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* Arg1 : And data
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* Arg2 : Or data
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*/
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Method (RAOW, 0x3, NotSerialized)
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{
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Local0 = Arg0
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Arg0 = Local0 & Arg1 | Arg2
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}
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/*
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* Clock Control
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* Arg0 - Clock number (0:IMGCLKOUT_0, etc)
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* Arg1 - Desired state (0:Disable, 1:Enable)
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*/
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Method(CLKC, 0x2, NotSerialized)
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{
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Switch (ToInteger (Arg0))
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{
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Case (0)
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{
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RAOW (CLK1, ~B_ICLK_PCR_REQUEST, Arg1 << 1)
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}
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Case (1)
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{
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RAOW (CLK2, ~B_ICLK_PCR_REQUEST, Arg1 << 1)
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}
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Case (2)
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{
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RAOW (CLK3, ~B_ICLK_PCR_REQUEST, Arg1 << 1)
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}
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Case (3)
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{
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RAOW (CLK4, ~B_ICLK_PCR_REQUEST, Arg1 << 1)
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}
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Case (4)
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{
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RAOW (CLK5, ~B_ICLK_PCR_REQUEST, Arg1 << 1)
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}
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Case (5)
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{
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RAOW (CLK6, ~B_ICLK_PCR_REQUEST, Arg1 << 1)
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}
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}
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}
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/*
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* Clock Frequency
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* Arg0 - Clock number (0:IMGCLKOUT_0, etc)
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* Arg1 - Clock frequency (0:24MHz, 1:19.2MHz)
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*/
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Method (CLKF, 0x2, NotSerialized)
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{
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Switch (ToInteger (Arg0))
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{
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Case (0)
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{
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RAOW (CLK1, ~B_ICLK_PCR_FREQUENCY, Arg1)
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}
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Case (1)
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{
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RAOW (CLK2, ~B_ICLK_PCR_FREQUENCY, Arg1)
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}
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Case (2)
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{
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RAOW (CLK3, ~B_ICLK_PCR_FREQUENCY, Arg1)
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}
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Case (3)
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{
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RAOW (CLK4, ~B_ICLK_PCR_FREQUENCY, Arg1)
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}
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Case (4)
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{
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RAOW (CLK5, ~B_ICLK_PCR_FREQUENCY, Arg1)
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}
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Case (5)
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{
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RAOW (CLK6, ~B_ICLK_PCR_FREQUENCY, Arg1)
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}
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}
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}
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/*
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* Clock control Method
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* Arg0: Clock source select(0: IMGCLKOUT_0, 1: IMGCLKOUT_1, 2: IMGCLKOUT_2, 3: IMGCLKOUT_3,
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* 4: IMGCLKOUT_4, 5: IMGCLKOUT_5)
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* Arg1: Clock Enable / Disable (0: Disable, 1: Enable)
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* Arg2: Select 24MHz / 19.2 MHz (0: 24MHz, 1: 19.2MHz)
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*/
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Method (MCCT, 0x3, NotSerialized)
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{
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CLKF (Arg0, Arg2)
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CLKC (Arg0, Arg1)
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}
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}
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@ -69,6 +69,12 @@ Device (SPI2)
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Name (_DDN, "Serial IO SPI Controller 2")
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}
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Device (SPI3)
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{
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Name (_ADR, 0x00130000)
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Name (_DDN, "Serial IO SPI Controller 3")
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}
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Device (UAR0)
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{
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Name (_ADR, 0x001e0000)
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2020 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Intel SMBus Controller 0:1f.4 */
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Device (SBUS)
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{
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Name (_ADR, 0x001f0004)
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}
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@ -25,8 +25,8 @@
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/* PCR access */
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#include <soc/intel/common/acpi/pcr.asl>
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/* eMMC, SD Card */
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#include "scs.asl"
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/* PCH clock */
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#include "camera_clock_ctl.asl"
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/* GPIO controller */
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#include "gpio.asl"
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@ -43,11 +43,11 @@
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/* Serial IO */
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#include "serialio.asl"
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/* SMBus 0:1f.4 */
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#include "smbus.asl"
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/* USB XHCI 0:14.0 */
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#include "xhci.asl"
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/* PCI _OSC */
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#include <soc/intel/common/acpi/pci_osc.asl>
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/* GBe 0:1f.6 */
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#include "pch_glan.asl"
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@ -53,19 +53,11 @@ Device (XHCI)
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Device (HS08) { Name (_ADR, 8) }
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Device (HS09) { Name (_ADR, 9) }
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Device (HS10) { Name (_ADR, 10) }
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Device (HS11) { Name (_ADR, 11) }
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Device (HS12) { Name (_ADR, 12) }
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/* USBr */
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Device (USR1) { Name (_ADR, 11) }
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Device (USR2) { Name (_ADR, 12) }
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/* USB3 */
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Device (SS01) { Name (_ADR, 13) }
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Device (SS02) { Name (_ADR, 14) }
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Device (SS03) { Name (_ADR, 15) }
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Device (SS04) { Name (_ADR, 16) }
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Device (SS05) { Name (_ADR, 17) }
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Device (SS06) { Name (_ADR, 18) }
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}
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}
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