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acpi: correct the processor devices scope 

The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here.

Additionally add processor scope patching for P-State SSDT created by
AGESA, becasue AGESA creates the tables with processors in \_PR scope.

TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are
no errors, decompile ACPI tables with acpica to check whether the
processor scope is correct and if IASL does not complain on wrong
checksum, run FWTS

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski 2020-03-20 13:56:46 +01:00 committed by Patrick Georgi
parent a956063e5f
commit 9550e97304
45 changed files with 189 additions and 74 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/cpu/amd/agesa/family14/acpi/cpu.asl
View File

@ -15,7 +15,7 @@
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Scope (\_SB) { /* define processor scope */
Device (C000) {
Name (_HID, "ACPI0007")
@ -26,4 +26,4 @@ Scope (\_PR) { /* define processor scope */
Name (_HID, "ACPI0007")
Name (_UID, 1)
}
} /* End _PR scope */
} /* End _SB scope */

4
src/cpu/amd/agesa/family15tn/acpi/cpu.asl
View File

@ -15,7 +15,7 @@
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Scope (\_SB) { /* define processor scope */
Device (P000) {
Name(_HID, "ACPI0007")
@ -56,4 +56,4 @@ Scope (\_PR) { /* define processor scope */
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
} /* End _PR scope */
} /* End _SB scope */

4
src/cpu/amd/agesa/family16kb/acpi/cpu.asl
View File

@ -15,7 +15,7 @@
* Processor Object
*
*/
Scope (\_PR) {/* define processor scope */
Scope (\_SB) {/* define processor scope */
Device (P000) {
Name(_HID, "ACPI0007")
Name(_UID, 0)
@ -55,4 +55,4 @@ Scope (\_PR) {/* define processor scope */
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
} /* End _PR scope */
} /* End _SB scope */

4
src/cpu/amd/pi/00630F01/acpi/cpu.asl
View File

@ -15,7 +15,7 @@
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Scope (\_SB) { /* define processor scope */
Device (P000) {
Name(_HID, "ACPI0007")
@ -56,4 +56,4 @@ Scope (\_PR) { /* define processor scope */
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
} /* End _PR scope */
} /* End _SB scope */

4
src/cpu/amd/pi/00660F01/acpi/cpu.asl
View File

@ -15,7 +15,7 @@
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Scope (\_SB) { /* define processor scope */
Device (P000) {
Name(_HID, "ACPI0007")
@ -56,4 +56,4 @@ Scope (\_PR) { /* define processor scope */
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
} /* End _PR scope */
} /* End _SB scope */

4
src/cpu/amd/pi/00730F01/acpi/cpu.asl
View File

@ -15,7 +15,7 @@
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Scope (\_SB) { /* define processor scope */
Device (P000) {
Name(_HID, "ACPI0007")
@ -56,4 +56,4 @@ Scope (\_PR) { /* define processor scope */
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
} /* End _PR scope */
} /* End _SB scope */

2
src/mainboard/amd/gardenia/dsdt.asl
View File

@ -39,7 +39,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu.asl>
/* Contains the supported sleep states for this chipset */

2
src/mainboard/amd/olivehill/dsdt.asl
View File

@ -34,7 +34,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */

2
src/mainboard/amd/padmelon/dsdt.asl
View File

@ -37,7 +37,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu.asl>
/* Contains the supported sleep states for this chipset */

2
src/mainboard/amd/parmer/dsdt.asl
View File

@ -34,7 +34,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
/* Describe the supported Sleep States for this Southbridge */

2
src/mainboard/amd/thatcher/acpi/cpstate.asl
View File

@ -21,7 +21,7 @@
#include <arch/acpi.h>
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
{
Scope (\_PR) {
Scope (\_SB) {
Device (CPU0) {
Name (_HID, "ACPI0007")
Name (_UID, 0)

2
src/mainboard/amd/thatcher/dsdt.asl
View File

@ -34,7 +34,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
/* Describe the supported Sleep States for this Southbridge */

2
src/mainboard/asrock/imb-a180/dsdt.asl
View File

@ -34,7 +34,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */

2
src/mainboard/asus/am1i-a/dsdt.asl
View File

@ -31,7 +31,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */

2
src/mainboard/asus/f2a85-m/acpi/cpstate.asl
View File

@ -21,7 +21,7 @@
#include <arch/acpi.h>
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
{
Scope (\_PR) {
Scope (\_SB) {
Device (CPU0) {
Name (_HID, "ACPI0007")
Name (_UID, 0)

2
src/mainboard/asus/f2a85-m/dsdt.asl
View File

@ -34,7 +34,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
/* Describe the supported Sleep States for this Southbridge */

2
src/mainboard/asus/p2b-ls/dsdt.asl
View File

@ -23,7 +23,7 @@
#include <arch/acpi.h>
DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1)
{
/* \_PR scope defining the main processor is generated in SSDT. */
/* \_SB scope defining the main processor is generated in SSDT. */
OperationRegion(X80, SystemIO, 0x80, 1)
Field(X80, ByteAcc, NoLock, Preserve)

2
src/mainboard/asus/p2b/dsdt.asl
View File

@ -23,7 +23,7 @@
#include <arch/acpi.h>
DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1)
{
/* \_PR scope defining the main processor is generated in SSDT. */
/* \_SB scope defining the main processor is generated in SSDT. */
OperationRegion(X80, SystemIO, 0x80, 1)
Field(X80, ByteAcc, NoLock, Preserve)

2
src/mainboard/bap/ode_e20XX/dsdt.asl
View File

@ -34,7 +34,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */

2
src/mainboard/bap/ode_e21XX/dsdt.asl
View File

@ -34,7 +34,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */

2
src/mainboard/biostar/a68n_5200/dsdt.asl
View File

@ -34,7 +34,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */

2
src/mainboard/biostar/am1ml/dsdt.asl
View File

@ -34,7 +34,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */

2
src/mainboard/gizmosphere/gizmo2/dsdt.asl
View File

@ -34,7 +34,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */

2
src/mainboard/google/kahlee/dsdt.asl
View File

@ -36,7 +36,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu.asl>
/* Contains the supported sleep states for this chipset */

2
src/mainboard/hp/abm/dsdt.asl
View File

@ -34,7 +34,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */

2
src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl
View File

@ -36,7 +36,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
/* Describe the supported Sleep States for this Southbridge */

2
src/mainboard/lenovo/g505s/dsdt.asl
View File

@ -36,7 +36,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
/* Describe the supported Sleep States for this Southbridge */

4
src/mainboard/lippert/frontrunner-af/dsdt.asl
View File

@ -56,7 +56,7 @@ DefinitionBlock (
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Scope (\_SB) { /* define processor scope */
Device (C000) {
Name (_HID, "ACPI0007")
Name (_UID, 0)
@ -73,7 +73,7 @@ DefinitionBlock (
Name (_HID, "ACPI0007")
Name (_UID, 3)
}
} /* End _PR scope */
} /* End _SB scope */
/* PIC IRQ mapping registers, C00h-C01h. */
OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)

4
src/mainboard/lippert/toucan-af/dsdt.asl
View File

@ -56,7 +56,7 @@ DefinitionBlock (
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Scope (\_SB) { /* define processor scope */
Device (C000) {
Name (_HID, "ACPI0007")
Name (_UID, 0)
@ -73,7 +73,7 @@ DefinitionBlock (
Name (_HID, "ACPI0007")
Name (_UID, 3)
}
} /* End _PR scope */
} /* End _SB scope */
/* PIC IRQ mapping registers, C00h-C01h. */
OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)

2
src/mainboard/msi/ms7721/acpi/cpstate.asl
View File

@ -21,7 +21,7 @@
#include <arch/acpi.h>
DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
{
Scope (\_PR) {
Scope (\_SB) {
Device (CPU0) {
Name (_HID, "ACPI0007")
Name (_UID, 0)

2
src/mainboard/msi/ms7721/dsdt.asl
View File

@ -31,7 +31,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
/* Describe the supported Sleep States for this Southbridge */

2
src/mainboard/pcengines/apu2/dsdt.asl
View File

@ -34,7 +34,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
/* Describe the processor tree (\_SB) */
#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */

18
src/northbridge/amd/agesa/family14/northbridge.c
View File

@ -710,6 +710,21 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
return (unsigned long)current;
}
static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
{
unsigned int len = ssdt->length - sizeof(acpi_header_t);
unsigned int i;
for (i = sizeof(acpi_header_t); i < len; i++) {
/* Search for _PR_ scope and replace it with _SB_ */
if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
*(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
}
/* Recalculate checksum */
ssdt->checksum = 0;
ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
}
static unsigned long agesa_write_acpi_tables(struct device *device,
unsigned long current,
acpi_rsdp_t *rsdp)
@ -774,6 +789,9 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
if (ssdt != NULL) {
hexdump(ssdt, ssdt->length);
patch_ssdt_processor_scope(ssdt);
hexdump(ssdt, ssdt->length);
memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *) current;
current += ssdt->length;

16
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@ -449,6 +449,21 @@ static void northbridge_fill_ssdt_generator(struct device *device)
acpigen_pop_len();
}
static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
{
unsigned int len = ssdt->length - sizeof(acpi_header_t);
unsigned int i;
for (i = sizeof(acpi_header_t); i < len; i++) {
/* Search for _PR_ scope and replace it with _SB_ */
if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
*(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
}
/* Recalculate checksum */
ssdt->checksum = 0;
ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
}
static unsigned long agesa_write_acpi_tables(struct device *device,
unsigned long current,
acpi_rsdp_t *rsdp)
@ -525,6 +540,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
if (ssdt != NULL) {
patch_ssdt_processor_scope(ssdt);
memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *) current;
current += ssdt->length;

16
src/northbridge/amd/agesa/family16kb/northbridge.c
View File

@ -449,6 +449,21 @@ static void northbridge_fill_ssdt_generator(struct device *device)
acpigen_pop_len();
}
static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
{
unsigned int len = ssdt->length - sizeof(acpi_header_t);
unsigned int i;
for (i = sizeof(acpi_header_t); i < len; i++) {
/* Search for _PR_ scope and replace it with _SB_ */
if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
*(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
}
/* Recalculate checksum */
ssdt->checksum = 0;
ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
}
static unsigned long agesa_write_acpi_tables(struct device *device,
unsigned long current,
acpi_rsdp_t *rsdp)
@ -525,6 +540,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
if (ssdt != NULL) {
patch_ssdt_processor_scope(ssdt);
memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *) current;
current += ssdt->length;

16
src/northbridge/amd/pi/00630F01/northbridge.c
View File

@ -447,6 +447,21 @@ static void northbridge_fill_ssdt_generator(struct device *device)
acpigen_pop_len();
}
static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
{
unsigned int len = ssdt->length - sizeof(acpi_header_t);
unsigned int i;
for (i = sizeof(acpi_header_t); i < len; i++) {
/* Search for _PR_ scope and replace it with _SB_ */
if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
*(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
}
/* Recalculate checksum */
ssdt->checksum = 0;
ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
}
static unsigned long agesa_write_acpi_tables(struct device *device,
unsigned long current,
acpi_rsdp_t *rsdp)
@ -521,6 +536,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
if (ssdt != NULL) {
patch_ssdt_processor_scope(ssdt);
memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *) current;
current += ssdt->length;

16
src/northbridge/amd/pi/00660F01/northbridge.c
View File

@ -435,6 +435,21 @@ static void northbridge_fill_ssdt_generator(struct device *device)
acpigen_pop_len();
}
static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
{
unsigned int len = ssdt->length - sizeof(acpi_header_t);
unsigned int i;
for (i = sizeof(acpi_header_t); i < len; i++) {
/* Search for _PR_ scope and replace it with _SB_ */
if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
*(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
}
/* Recalculate checksum */
ssdt->checksum = 0;
ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
}
static unsigned long agesa_write_acpi_tables(struct device *device,
unsigned long current,
acpi_rsdp_t *rsdp)
@ -511,6 +526,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
if (ssdt != NULL) {
patch_ssdt_processor_scope(ssdt);
memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *) current;
current += ssdt->length;

16
src/northbridge/amd/pi/00730F01/northbridge.c
View File

@ -671,6 +671,21 @@ static void northbridge_fill_ssdt_generator(struct device *device)
acpigen_pop_len();
}
static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
{
unsigned int len = ssdt->length - sizeof(acpi_header_t);
unsigned int i;
for (i = sizeof(acpi_header_t); i < len; i++) {
/* Search for _PR_ scope and replace it with _SB_ */
if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
*(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
}
/* Recalculate checksum */
ssdt->checksum = 0;
ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
}
static unsigned long agesa_write_acpi_tables(struct device *device,
unsigned long current,
acpi_rsdp_t *rsdp)
@ -741,6 +756,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
if (ssdt != NULL) {
patch_ssdt_processor_scope(ssdt);
memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *) current;
current += ssdt->length;

6
src/soc/amd/picasso/acpi.c
View File

@ -236,13 +236,13 @@ void generate_cpu_entries(struct device *device)
int cores, cpu;
cores = get_cpu_count();
printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores);
/* Generate BSP \_PR.P000 */
/* Generate BSP \_SB.P000 */
acpigen_write_processor(0, ACPI_GPE0_BLK, 6);
acpigen_pop_len();
/* Generate AP \_PR.Pxxx */
/* Generate AP \_SB.Pxxx */
for (cpu = 1; cpu < cores; cpu++) {
acpigen_write_processor(cpu, 0, 0);
acpigen_pop_len();

22
src/soc/amd/picasso/acpi/cpu.asl
View File

@ -21,14 +21,14 @@ Method (PNOT)
* Processor Object
*/
/* These devices are created at runtime */
External (\_PR.P000, DeviceObj)
External (\_PR.P001, DeviceObj)
External (\_PR.P002, DeviceObj)
External (\_PR.P003, DeviceObj)
External (\_PR.P004, DeviceObj)
External (\_PR.P005, DeviceObj)
External (\_PR.P006, DeviceObj)
External (\_PR.P007, DeviceObj)
External (\_SB.P000, DeviceObj)
External (\_SB.P001, DeviceObj)
External (\_SB.P002, DeviceObj)
External (\_SB.P003, DeviceObj)
External (\_SB.P004, DeviceObj)
External (\_SB.P005, DeviceObj)
External (\_SB.P006, DeviceObj)
External (\_SB.P007, DeviceObj)
/* Return a package containing enabled processor entries */
Method (PPKG)
@ -36,13 +36,13 @@ Method (PPKG)
If (LGreaterEqual (\PCNT, 2)) {
Return (Package ()
{
\_PR.P000,
\_PR.P001
\_SB.P000,
\_SB.P001
})
} Else {
Return (Package ()
{
\_PR.P000
\_SB.P000
})
}
}

2
src/soc/amd/picasso/southbridge.c
View File

@ -367,7 +367,7 @@ static void sb_init_acpi_ports(void)
pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
/* CpuControl is in \_PR.CP00, 6 bytes */
/* CpuControl is in \_SB.CP00, 6 bytes */
cst_addr.hi = 0;
cst_addr.lo = ACPI_CPU_CONTROL;
wrmsr(CSTATE_BASE_REG, cst_addr);

6
src/soc/amd/stoneyridge/acpi.c
View File

@ -241,13 +241,13 @@ void generate_cpu_entries(struct device *device)
cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK;
cores++; /* number of cores is CmpCap+1 */
printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores);
/* Generate BSP \_PR.P000 */
/* Generate BSP \_SB.P000 */
acpigen_write_processor(0, ACPI_GPE0_BLK, 6);
acpigen_pop_len();
/* Generate AP \_PR.Pxxx */
/* Generate AP \_SB.Pxxx */
for (cpu = 1; cpu < cores; cpu++) {
acpigen_write_processor(cpu, 0, 0);
acpigen_pop_len();

30
src/soc/amd/stoneyridge/acpi/cpu.asl
View File

@ -21,14 +21,14 @@ Method (PNOT)
* Processor Object
*/
/* These devices are created at runtime */
External (\_PR.P000, DeviceObj)
External (\_PR.P001, DeviceObj)
External (\_PR.P002, DeviceObj)
External (\_PR.P003, DeviceObj)
External (\_PR.P004, DeviceObj)
External (\_PR.P005, DeviceObj)
External (\_PR.P006, DeviceObj)
External (\_PR.P007, DeviceObj)
External (\_SB.P000, DeviceObj)
External (\_SB.P001, DeviceObj)
External (\_SB.P002, DeviceObj)
External (\_SB.P003, DeviceObj)
External (\_SB.P004, DeviceObj)
External (\_SB.P005, DeviceObj)
External (\_SB.P006, DeviceObj)
External (\_SB.P007, DeviceObj)
/* Return a package containing enabled processor entries */
Method (PPKG)
@ -36,21 +36,21 @@ Method (PPKG)
If (LGreaterEqual (\PCNT, 4)) {
Return (Package ()
{
\_PR.P000,
\_PR.P001,
\_PR.P002,
\_PR.P003
\_SB.P000,
\_SB.P001,
\_SB.P002,
\_SB.P003
})
} ElseIf (LGreaterEqual (\PCNT, 2)) {
Return (Package ()
{
\_PR.P000,
\_PR.P001
\_SB.P000,
\_SB.P001
})
} Else {
Return (Package ()
{
\_PR.P000
\_SB.P000
})
}
}

17
src/soc/amd/stoneyridge/northbridge.c
View File

@ -227,6 +227,22 @@ static void northbridge_fill_ssdt_generator(struct device *device)
acpigen_pop_len();
}
static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
{
unsigned int len = ssdt->length - sizeof(acpi_header_t);
unsigned int i;
for (i = sizeof(acpi_header_t); i < len; i++) {
/* Search for _PR_ scope and replace it with _SB_ */
if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
*(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
}
/* Recalculate checksum */
ssdt->checksum = 0;
ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
}
static unsigned long agesa_write_acpi_tables(struct device *device,
unsigned long current,
acpi_rsdp_t *rsdp)
@ -322,6 +338,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE);
if (ssdt != NULL) {
patch_ssdt_processor_scope(ssdt);
memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *)current;
current += ssdt->length;

2
src/soc/amd/stoneyridge/southbridge.c
View File

@ -488,7 +488,7 @@ static void sb_init_acpi_ports(void)
pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
/* CpuControl is in \_PR.CP00, 6 bytes */
/* CpuControl is in \_SB.CP00, 6 bytes */
pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL);
if (CONFIG(HAVE_SMI_HANDLER)) {