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soc/amd/cezanne: Update GPP clk req code to use ARRAY_SIZE 

Currently the GPP clk req configuration code assumes that the size of
the config array is `GPP_CLK_OUTPUT_COUNT`. This commit changes that
code to use the `ARRAY_SIZE` macro instead.

BRANCH=guybrush
BUG=b:250009974
TEST=Ran on nipperkin device, verified that clk req settings are
correct.

Change-Id: I3ff555843c6f5aa38acd8300e0dc2da4e33fb4b7
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Robert Zieba 2022-10-25 10:30:14 -06:00 committed by Felix Held
parent 5a040d6662
commit 956432cbb7
1 changed files with 2 additions and 1 deletions
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3
src/soc/amd/cezanne/fch.c
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@ -153,7 +153,8 @@ static void gpp_clk_setup(void)
uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], GPP_CLK_OUTPUT_COUNT); pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0],
ARRAY_SIZE(cfg->gpp_clk_config));
for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);