x86: link romstage and ramstage with 1 file

To reduce file clutter merge romstage.ld and ramstage.ld
into a single memlayout.ld. The naming is consistent with
other architectures and chipsets for their linker script
names. The cache-as-ram linking rules are put into a separate
file such that other rules can be applied for future verstage
support.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi and dmp/vortex86ex.

Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Reviewed-on: http://review.coreboot.org/11521
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/arch/x86/Makefile.inc

@@ -113,7 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-y += romstage.ld
+romstage-y += memlayout.ld
 
 # Chipset specific assembly stubs in the romstage program flow. Certain
 # boards have more than one assembly stub so collect those and put them
@@ -192,7 +192,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 	$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
 
-$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
+$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	rm -f $@
 	printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
@@ -294,11 +294,11 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 else
 
-ramstage-y += ramstage.ld
+ramstage-y += memlayout.ld
 
-$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
+$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld
+	$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
 
 endif
 

src/arch/x86/car.ld

@@ -19,14 +19,7 @@
  * Foundation, Inc.
  */
 
-#include <memlayout.h>
+/* This file is included inside a SECTIONS block */
-#include <arch/header.ld>
-
-SECTIONS
-{
-	/* The 1M size is not allocated. It's just for basic size checking. */
-	ROMSTAGE(ROMSTAGE_BASE, 1M)
-
 . = CONFIG_DCACHE_RAM_BASE;
 .car.data . (NOLOAD) : {
 	_car_data_start = .;
@@ -56,4 +49,3 @@ SECTIONS
 }
 
 _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-}

src/arch/x86/memlayout.ld

@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+SECTIONS
+{
+	/*
+	 * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively
+	 * like other architectures/chipsets it's not possible because of
+	 * the linking games played during romstage creation by trying
+	 * to find the final landing place in CBFS for XIP. Therefore,
+	 * conditionalize with macros.
+	 */
+#if ENV_RAMSTAGE
+	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
+
+#elif ENV_ROMSTAGE
+	/* The 1M size is not allocated. It's just for basic size checking. */
+	ROMSTAGE(ROMSTAGE_BASE, 1M)
+
+	/* Pull in the cache-as-ram rules. */
+	#include "car.ld"
+#endif
+}

src/arch/x86/ramstage.ld

@@ -1,7 +0,0 @@
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
-}