x86: link romstage and ramstage with 1 file
To reduce file clutter merge romstage.ld and ramstage.ld into a single memlayout.ld. The naming is consistent with other architectures and chipsets for their linker script names. The cache-as-ram linking rules are put into a separate file such that other rules can be applied for future verstage support. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and dmp/vortex86ex. Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11521 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin
parent
dde7629e9c
commit
956c4f2d4c
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@ -113,7 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
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ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
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romstage-y += romstage.ld
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romstage-y += memlayout.ld
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# Chipset specific assembly stubs in the romstage program flow. Certain
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# boards have more than one assembly stub so collect those and put them
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@ -192,7 +192,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms
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@printf " LINK $(subst $(obj)/,,$(@))\n"
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$(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
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$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld
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$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld
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@printf " GEN $(subst $(obj)/,,$(@))\n"
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rm -f $@
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printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp
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@ -294,11 +294,11 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
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else
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ramstage-y += ramstage.ld
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ramstage-y += memlayout.ld
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$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
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$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld
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@printf " CC $(subst $(obj)/,,$(@))\n"
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$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld
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$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld
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endif
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@ -19,41 +19,33 @@
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* Foundation, Inc.
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*/
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#include <memlayout.h>
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#include <arch/header.ld>
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SECTIONS
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{
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/* The 1M size is not allocated. It's just for basic size checking. */
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ROMSTAGE(ROMSTAGE_BASE, 1M)
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. = CONFIG_DCACHE_RAM_BASE;
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.car.data . (NOLOAD) : {
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_car_data_start = .;
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/* This file is included inside a SECTIONS block */
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. = CONFIG_DCACHE_RAM_BASE;
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.car.data . (NOLOAD) : {
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_car_data_start = .;
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#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
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TIMESTAMP(., 0x100)
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TIMESTAMP(., 0x100)
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#endif
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*(.car.global_data);
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. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
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_car_data_end = .;
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*(.car.global_data);
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. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
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_car_data_end = .;
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PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
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}
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/* Global variables are not allowed in romstage
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* This section is checked during stage creation to ensure
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* that there are no global variables present
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*/
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. = 0xffffff00;
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.illegal_globals . : {
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*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
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*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
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*(.bss)
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*(.bss.*)
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*(.sbss)
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*(.sbss.*)
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}
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_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
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PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00))
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}
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/* Global variables are not allowed in romstage
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* This section is checked during stage creation to ensure
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* that there are no global variables present
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*/
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. = 0xffffff00;
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.illegal_globals . : {
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*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
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*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
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*(.bss)
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*(.bss.*)
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*(.sbss)
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*(.sbss.*)
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}
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_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
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@ -0,0 +1,42 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <memlayout.h>
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#include <arch/header.ld>
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SECTIONS
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{
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/*
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* It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively
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* like other architectures/chipsets it's not possible because of
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* the linking games played during romstage creation by trying
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* to find the final landing place in CBFS for XIP. Therefore,
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* conditionalize with macros.
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*/
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#if ENV_RAMSTAGE
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RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
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#elif ENV_ROMSTAGE
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/* The 1M size is not allocated. It's just for basic size checking. */
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ROMSTAGE(ROMSTAGE_BASE, 1M)
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/* Pull in the cache-as-ram rules. */
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#include "car.ld"
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#endif
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}
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@ -1,7 +0,0 @@
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#include <memlayout.h>
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#include <arch/header.ld>
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SECTIONS
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{
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RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
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}
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