sb/intel/common: SMBus setup_command()
Implements the common parts of any SMBus transaction with a stub to log and recover (TBD) from timeout errors. Bits in SMBHSTCTL register are no longer preserved between transactions. Change-Id: I7ce14d3e895c30d595a94ce29ce0dc8cf51eb453 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/21118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
Patrick Georgi
parent
4c2ce72341
commit
957511cd92
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@ -53,6 +53,10 @@
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#define SMBHSTSTS_INTR (1 << 1)
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#define SMBHSTSTS_HOST_BUSY (1 << 0)
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/* For SMBXMITADD register. */
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#define XMIT_WRITE(dev) (((dev) << 1) | 0)
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#define XMIT_READ(dev) (((dev) << 1) | 1)
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#define SMBUS_TIMEOUT (10 * 1000 * 100)
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#define SMBUS_BLOCK_MAXLEN 32
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@ -61,31 +65,40 @@ static void smbus_delay(void)
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inb(0x80);
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}
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static int smbus_wait_until_ready(u16 smbus_base)
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static int recover_master(int smbus_base, int ret)
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{
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unsigned int loops = SMBUS_TIMEOUT;
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unsigned char byte;
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do {
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smbus_delay();
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if (--loops == 0)
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break;
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byte = inb(smbus_base + SMBHSTSTAT);
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} while (byte & SMBHSTSTS_HOST_BUSY);
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return loops ? 0 : -1;
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/* TODO: Depending of the failure, drive KILL transaction
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* or force soft reset on SMBus master controller.
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*/
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printk(BIOS_ERR, "SMBus: Fatal master timeout (%d)\n", ret);
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return ret;
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}
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static int smbus_wait_until_done(u16 smbus_base)
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static int setup_command(unsigned int smbus_base, u8 ctrl, u8 xmitadd)
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{
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unsigned int loops = SMBUS_TIMEOUT;
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unsigned char byte;
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u8 host_busy;
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do {
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smbus_delay();
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if (--loops == 0)
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break;
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byte = inb(smbus_base + SMBHSTSTAT);
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} while ((byte & SMBHSTSTS_HOST_BUSY)
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|| (byte & ~(SMBHSTSTS_INUSE_STS | SMBHSTSTS_HOST_BUSY)) == 0);
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return loops ? 0 : -1;
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host_busy = inb(smbus_base + SMBHSTSTAT) & SMBHSTSTS_HOST_BUSY;
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} while (--loops && host_busy);
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if (loops == 0)
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return recover_master(smbus_base,
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SMBUS_WAIT_UNTIL_READY_TIMEOUT);
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/* Clear any lingering errors, so the transaction will run. */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Set up transaction */
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/* Disable interrupts */
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outb(ctrl, (smbus_base + SMBHSTCTL));
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/* Set the device I'm talking to. */
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outb(xmitadd, smbus_base + SMBXMITADD);
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return 0;
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}
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static int smbus_wait_until_active(u16 smbus_base)
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@ -103,27 +116,34 @@ static int smbus_wait_until_active(u16 smbus_base)
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return loops ? 0 : -1;
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}
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static int smbus_wait_until_done(u16 smbus_base)
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{
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unsigned int loops = SMBUS_TIMEOUT;
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unsigned char byte;
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do {
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smbus_delay();
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if (--loops == 0)
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break;
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byte = inb(smbus_base + SMBHSTSTAT);
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} while ((byte & SMBHSTSTS_HOST_BUSY)
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|| (byte & ~(SMBHSTSTS_INUSE_STS | SMBHSTSTS_HOST_BUSY)) == 0);
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return loops ? 0 : -1;
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}
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int do_smbus_read_byte(unsigned int smbus_base, u8 device,
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unsigned int address)
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{
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int ret;
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unsigned char status;
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unsigned char byte;
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if (smbus_wait_until_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Set up transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & ~SMBHSTCNT_INTREN,
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smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
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/* Set up for a byte data read. */
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ret = setup_command(smbus_base, I801_BYTE_DATA, XMIT_READ(device));
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if (ret < 0)
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return ret;
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/* Set the command/address... */
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outb(address & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a byte data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | I801_BYTE_DATA,
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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outb(address, smbus_base + SMBHSTCMD);
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/* Clear the data byte... */
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outb(0, smbus_base + SMBHSTDAT0);
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@ -156,25 +176,17 @@ int do_smbus_write_byte(unsigned int smbus_base, u8 device,
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unsigned int address, unsigned int data)
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{
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unsigned char status;
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int ret;
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if (smbus_wait_until_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Set up for a byte data write. */
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ret = setup_command(smbus_base, I801_BYTE_DATA, XMIT_WRITE(device));
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if (ret < 0)
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return ret;
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/* Set up transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & ~SMBHSTCNT_INTREN,
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smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(address & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a byte data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | I801_BYTE_DATA,
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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outb(address, smbus_base + SMBHSTCMD);
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/* Clear the data byte... */
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/* Set the data byte... */
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outb(data, smbus_base + SMBHSTDAT0);
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/* Start the command */
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@ -205,27 +217,19 @@ int do_smbus_block_read(unsigned int smbus_base, u8 device, u8 cmd,
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unsigned int max_bytes, u8 *buf)
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{
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u8 status;
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int slave_bytes;
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int ret, slave_bytes;
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int bytes_read = 0;
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unsigned int loops = SMBUS_TIMEOUT;
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if (smbus_wait_until_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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max_bytes = MIN(SMBUS_BLOCK_MAXLEN, max_bytes);
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/* Set up transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & ~SMBHSTCNT_INTREN,
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smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
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/* Set up for a block data read. */
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ret = setup_command(smbus_base, I801_BLOCK_DATA, XMIT_READ(device));
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if (ret < 0)
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return ret;
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/* Set the command/address... */
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outb(cmd & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a block data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xc3) | I801_BLOCK_DATA,
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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outb(cmd, smbus_base + SMBHSTCMD);
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/* Reset number of bytes to transfer so we notice later it
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* was really updated with the transaction. */
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@ -279,30 +283,21 @@ int do_smbus_block_write(unsigned int smbus_base, u8 device, u8 cmd,
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const unsigned int bytes, const u8 *buf)
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{
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u8 status;
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int bytes_sent = 0;
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int ret, bytes_sent = 0;
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unsigned int loops = SMBUS_TIMEOUT;
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if (bytes > SMBUS_BLOCK_MAXLEN)
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return SMBUS_ERROR;
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if (smbus_wait_until_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Set up for a block data write. */
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ret = setup_command(smbus_base, I801_BLOCK_DATA, XMIT_WRITE(device));
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if (ret < 0)
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return ret;
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/* Set up transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & ~SMBHSTCNT_INTREN,
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smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(cmd & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a block data write */
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outb((inb(smbus_base + SMBHSTCTL) & 0xc3) | I801_BLOCK_DATA,
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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outb(cmd, smbus_base + SMBHSTCMD);
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/* set number of bytes to transfer */
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/* Set number of bytes to transfer. */
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outb(bytes, smbus_base + SMBHSTDAT0);
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/* Send first byte from buffer, bytes_sent increments after
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@ -354,27 +349,23 @@ int do_i2c_block_read(unsigned int smbus_base, u8 device,
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unsigned int offset, const unsigned int bytes, u8 *buf)
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{
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u8 status;
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int bytes_read = 0;
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int ret, bytes_read = 0;
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unsigned int loops = SMBUS_TIMEOUT;
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if (smbus_wait_until_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Set upp transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & SMBHSTCNT_INTREN,
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smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb((device & 0x7f) << 1, smbus_base + SMBXMITADD);
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/* Set up for a i2c block data read.
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*
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* FIXME: Address parameter changes to XMIT_READ(device) with
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* some revision of PCH. Presumably hardware revisions that
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* do not have i2c block write support internally set LSB.
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*/
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ret = setup_command(smbus_base, I801_I2C_BLOCK_DATA,
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XMIT_WRITE(device));
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if (ret < 0)
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return ret;
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/* device offset */
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outb(offset, smbus_base + SMBHSTDAT1);
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/* Set up for a i2c block data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xc3) | I801_I2C_BLOCK_DATA,
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | SMBHSTCNT_START),
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smbus_base + SMBHSTCTL);
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