diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c
index e813f786e6..32f66af190 100644
--- a/src/cpu/x86/smm/smm_module_handler.c
+++ b/src/cpu/x86/smm/smm_module_handler.c
@@ -74,14 +74,6 @@ void io_trap_handler(int smif)
 	printk(BIOS_DEBUG, "Unknown function\n");
 }
 
-/**
- * @brief Set the EOS bit
- */
-static void smi_set_eos(void)
-{
-	southbridge_smi_set_eos();
-}
-
 static u32 pci_orig;
 
 /**
@@ -196,7 +188,7 @@ asmlinkage void smm_handler_start(void *arg)
 	smi_release_lock();
 
 	/* De-assert SMI# signal to allow another SMI */
-	smi_set_eos();
+	southbridge_smi_set_eos();
 }
 
 RMODULE_ENTRY(smm_handler_start);
diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c
index 02a8375e9a..a43b95c69f 100644
--- a/src/southbridge/intel/common/pmutil.c
+++ b/src/southbridge/intel/common/pmutil.c
@@ -176,18 +176,6 @@ void dump_tco_status(u32 tco_sts)
 	printk(BIOS_DEBUG, "\n");
 }
 
-/**
- * @brief Set the EOS bit
- */
-void smi_set_eos(void)
-{
-	u8 reg8;
-
-	reg8 = read_pmbase8(SMI_EN);
-	reg8 |= EOS;
-	write_pmbase8(SMI_EN, reg8);
-}
-
 void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
 {
 	int i;
diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h
index c9cf544f4e..ff7b5e85e6 100644
--- a/src/southbridge/intel/common/pmutil.h
+++ b/src/southbridge/intel/common/pmutil.h
@@ -120,7 +120,6 @@ void dump_smi_status(u32 smi_sts);
 u32 reset_smi_status(void);
 void gpe0_mask(u32 clr, u32 set);
 void alt_gpi_mask(u16 clr, u16 set);
-void smi_set_eos(void);
 void dump_alt_gp_smi_status(u16 alt_gp_smi_sts);
 u16 reset_alt_gp_smi_status(void);
 void dump_all_status(void);