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northbridge/amd/amdmct: Reduce maximum number of DDR3 DIMMs 

CAR space on certain platforms is nearly full.  This prevents the
addition of necessary RAM initialization features such as x4 DIMM
support.  As the DIMM SPD cache uses a sizeable amount of CAR RAM,
reducing it would free up a significant amount of CAR RAM.

DDR3-based AMD platforms only support up to 3 physical DIMMs on
each channel (6 per node).  Reduce the maximum number of DIMMs
on a node from 8 to 6 accordingly.

Change-Id: I38def86da76fc622785318c825670209b2ac9017
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12107
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Timothy Pearson 2015-10-20 21:32:09 -05:00 committed by Stefan Reinauer
parent 21be0d2bd0
commit 9597790571
1 changed files with 5 additions and 1 deletions
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6
src/northbridge/amd/amdmct/wrappers/mcti.h
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@ -47,7 +47,11 @@ UPDATE AS NEEDED
#endif #endif
#ifndef MAX_DIMMS_SUPPORTED #ifndef MAX_DIMMS_SUPPORTED
#define MAX_DIMMS_SUPPORTED 8 #if IS_ENABLED(CONFIG_DIMM_DDR3)
#define MAX_DIMMS_SUPPORTED 6
#else
#define MAX_DIMMS_SUPPORTED 8
#endif
#endif #endif
#ifndef MAX_CS_SUPPORTED #ifndef MAX_CS_SUPPORTED