diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index f97b2f2e06..4ced781ca7 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -108,8 +108,6 @@ config CPU_SPECIFIC_OPTIONS
 	select UDELAY_TSC
 	select UDK_202005_BINDING
 	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
-	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
-	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
 
 config ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR
 	bool
diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c
index b31395d74a..7498f3f7fa 100644
--- a/src/soc/intel/alderlake/finalize.c
+++ b/src/soc/intel/alderlake/finalize.c
@@ -80,6 +80,13 @@ static void sa_finalize(void)
 		sa_lock_pam();
 }
 
+static void heci_finalize(void)
+{
+	heci_set_to_d0i3();
+	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
+		heci1_disable();
+}
+
 static void soc_finalize(void *unused)
 {
 	printk(BIOS_DEBUG, "Finalizing chipset.\n");
@@ -88,9 +95,9 @@ static void soc_finalize(void *unused)
 	apm_control(APM_CNT_FINALIZE);
 	tbt_finalize();
 	sa_finalize();
-	heci_set_to_d0i3();
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
-		heci1_disable();
+	if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
+			 CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
+		heci_finalize();
 
 	/* Indicate finalize step with post code */
 	post_code(POST_OS_BOOT);