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sb/intel/*/nvs: Rename register 

Rename register to match recent intel models.
Required for Lenovo H8 to operate on all generations.

Change-Id: I48a869adb1da2e33156968c4b7597edf99902c1a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Patrick Rudolph 2017-06-11 17:05:17 +02:00
parent 3f3025d7f1
commit 959dfc1261
4 changed files with 8 additions and 8 deletions
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4
src/southbridge/intel/i82801gx/acpi/globalnvs.asl
View File

@ -50,11 +50,11 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* Thermal policy */
Offset (0x14),
ACTT, 8, // 0x14 - active trip point
PSVT, 8, // 0x15 - passive trip point
TPSV, 8, // 0x15 - passive trip point
TC1V, 8, // 0x16 - passive trip point TC1
TC2V, 8, // 0x17 - passive trip point TC2
TSPV, 8, // 0x18 - passive trip point TSP
CRTT, 8, // 0x19 - critical trip point
TCRT, 8, // 0x19 - critical trip point
DTSE, 8, // 0x1a - Digital Thermal Sensor enable
DTS1, 8, // 0x1b - DT sensor 1
DTS2, 8, // 0x1c - DT sensor 2

4
src/southbridge/intel/i82801gx/nvs.h
View File

@ -35,11 +35,11 @@ typedef struct {
u8 dckn; /* 0x13 - PCIe docking state */
/* Thermal policy */
u8 actt; /* 0x14 - active trip point */
u8 psvt; /* 0x15 - passive trip point */
u8 tpsv; /* 0x15 - passive trip point */
u8 tc1v; /* 0x16 - passive trip point TC1 */
u8 tc2v; /* 0x17 - passive trip point TC2 */
u8 tspv; /* 0x18 - passive trip point TSP */
u8 crtt; /* 0x19 - critical trip point */
u8 tcrt; /* 0x19 - critical trip point */
u8 dtse; /* 0x1a - Digital Thermal Sensor enable */
u8 dts1; /* 0x1b - DT sensor 1 */
u8 dts2; /* 0x1c - DT sensor 2 */

4
src/southbridge/intel/i82801ix/acpi/globalnvs.asl
View File

@ -51,11 +51,11 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* Thermal policy */
Offset (0x14),
ACTT, 8, // 0x14 - active trip point
PSVT, 8, // 0x15 - passive trip point
TPSV, 8, // 0x15 - passive trip point
TC1V, 8, // 0x16 - passive trip point TC1
TC2V, 8, // 0x17 - passive trip point TC2
TSPV, 8, // 0x18 - passive trip point TSP
CRTT, 8, // 0x19 - critical trip point
TCRT, 8, // 0x19 - critical trip point
DTSE, 8, // 0x1a - Digital Thermal Sensor enable
DTS1, 8, // 0x1b - DT sensor 1
DTS2, 8, // 0x1c - DT sensor 2

4
src/southbridge/intel/i82801ix/nvs.h
View File

@ -35,11 +35,11 @@ typedef struct {
u8 dckn; /* 0x13 - PCIe docking state */
/* Thermal policy */
u8 actt; /* 0x14 - active trip point */
u8 psvt; /* 0x15 - passive trip point */
u8 tpsv; /* 0x15 - passive trip point */
u8 tc1v; /* 0x16 - passive trip point TC1 */
u8 tc2v; /* 0x17 - passive trip point TC2 */
u8 tspv; /* 0x18 - passive trip point TSP */
u8 crtt; /* 0x19 - critical trip point */
u8 tcrt; /* 0x19 - critical trip point */
u8 dtse; /* 0x1a - Digital Thermal Sensor enable */
u8 dts1; /* 0x1b - DT sensor 1 */
u8 dts2; /* 0x1c - DT sensor 2 */